b587a409a3
In order to implement a pass-through RAM Monitor model, we will want to support a variable number of inputs and outputs with BOTH different manager and client parameters on each bundle.
19 lines
794 B
Scala
19 lines
794 B
Scala
package uncore
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import Chisel._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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package object tilelink2
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{
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type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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type IntBaseNode = BaseNode[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
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case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
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case _ => ""
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}
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}
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