Andrew Waterman 0c50bfcfb3 Work around more zero-width wire cases

2016-05-25 21:47:48 -07:00

..

arbiter.scala

Don't rely on tag value for nacks

2016-05-24 15:05:41 -07:00

btb.scala

Remove dead code from BTB

2016-04-27 00:28:12 -07:00

consts.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

csr.scala

Remove most of mstatus when user mode isn't supported

2016-05-25 15:37:32 -07:00

dcache.scala

Work around lack of zero-width wires in D$

2016-05-25 19:44:31 -07:00

decode.scala

Use Seq, not Iterable, when traversal order matters

2015-07-29 00:24:58 -07:00

dma.scala

get rid of unused imports

2016-05-02 18:23:46 -07:00

dpath_alu.scala

Improve ALU QoR

2016-01-20 17:42:31 -08:00

fpu.scala

Added Field[Int] to SFMALatency/DFMALatency params

2016-04-06 14:50:57 -07:00

frontend.scala

Support larger I$ sets when VM is disabled

2016-05-24 15:44:59 -07:00

icache.scala

Support larger I$ sets when VM is disabled

2016-05-24 15:44:59 -07:00

idecode.scala

Don't include RV64 instructions in RV32 decode table

2016-05-25 14:26:45 -07:00

instructions.scala

ERET -> xRET; remove mcfgaddr

2016-04-30 17:32:51 -07:00

multiplier.scala

Remove unnecessary muxes in RV32 MulDiv

2016-05-25 14:27:02 -07:00

nbdcache.scala

Work around more zero-width wire cases

2016-05-25 21:47:48 -07:00

package.scala

make mtvec configurable and writeable

2016-01-29 14:51:56 -08:00

ptw.scala

Handle invalidate_lr in cache arbiter, not tile

2016-04-27 11:22:04 -07:00

rocc.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

rocket.scala

Remove most of mstatus when user mode isn't supported

2016-05-25 15:37:32 -07:00

tile.scala

Instantiate blocking D$ when NMSHRS=0

2016-05-24 15:05:41 -07:00

tlb.scala

MPRV takes effect regardless of privilege mode

2016-05-02 19:53:25 -07:00

util.scala

Avoid needless Vec generation

2016-04-27 00:28:39 -07:00