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rocket-chip/src/main/scala/rocket
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Andrew Waterman 4cfae27efd
Implement Hauser misa.C misalignment proposal (#1301) 
See 0472bcdd16

- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked in decode
 		2018-03-21 23:42:01 -07:00
..
ALU.scala Rationalize ALU function encoding 2018-02-06 14:00:37 -08:00
AMOALU.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
BTB.scala coreplex => subsystem 2018-02-21 14:42:24 -08:00
Breakpoint.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
BusErrorUnit.scala RegFieldDesc: reserved omits () 2018-03-12 08:24:36 -07:00
CSR.scala Implement Hauser misa.C misalignment proposal (#1301) 2018-03-21 23:42:01 -07:00
Consts.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
DCache.scala rocket: make RocketTileParams trivial to serialize 2018-03-20 11:25:02 -07:00
Decode.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Events.scala Add method to print perf events 2017-07-25 15:19:16 -07:00
Frontend.scala Bump chisel and firrtl (#1232) 2018-03-01 15:19:12 -08:00
HellaCache.scala rocket: make RocketTileParams trivial to serialize 2018-03-20 11:25:02 -07:00
HellaCacheArbiter.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
IBuf.scala Improve frontend branch prediction 2017-11-09 00:00:56 -08:00
ICache.scala rocket: make RocketTileParams trivial to serialize 2018-03-20 11:25:02 -07:00
IDecode.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Instructions.scala Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Multiplier.scala Teach MulDiv to do either mul-only or div-only by setting unroll=0 2018-02-06 14:03:17 -08:00
NBDcache.scala rocket: make RocketTileParams trivial to serialize 2018-03-20 11:25:02 -07:00
PMP.scala Move microarchitecture-neutral params from Rocket to Core 2017-10-03 17:34:18 -07:00
PTW.scala coreplex => subsystem 2018-02-21 14:42:24 -08:00
RVC.scala Expand C.UNIMP correctly (#1052) 2017-10-12 14:00:14 -07:00
RocketCore.scala Implement Hauser misa.C misalignment proposal (#1301) 2018-03-21 23:42:01 -07:00
ScratchpadSlavePort.scala tile: cake reduction 2018-01-02 17:49:08 -08:00
SimpleHellaCacheIF.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
TLB.scala coreplex => subsystem 2018-02-21 14:42:24 -08:00
TLBPermissions.scala rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
package.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00