100 lines
2.9 KiB
Scala
100 lines
2.9 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.tile.CoreModule
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object ALU
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{
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val SZ_ALU_FN = 4
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def FN_X = BitPat("b????")
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def FN_ADD = UInt(0)
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def FN_SL = UInt(1)
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def FN_SEQ = UInt(2)
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def FN_SNE = UInt(3)
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def FN_XOR = UInt(4)
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def FN_SR = UInt(5)
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def FN_OR = UInt(6)
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def FN_AND = UInt(7)
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def FN_SUB = UInt(10)
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def FN_SRA = UInt(11)
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def FN_SLT = UInt(12)
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def FN_SGE = UInt(13)
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def FN_SLTU = UInt(14)
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def FN_SGEU = UInt(15)
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def FN_DIV = FN_XOR
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def FN_DIVU = FN_SR
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def FN_REM = FN_OR
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def FN_REMU = FN_AND
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def FN_MUL = FN_ADD
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def FN_MULH = FN_SL
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def FN_MULHSU = FN_SEQ
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def FN_MULHU = FN_SNE
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def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0)
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def isSub(cmd: UInt) = cmd(3)
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def isCmp(cmd: UInt) = cmd >= FN_SLT
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def cmpUnsigned(cmd: UInt) = cmd(1)
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def cmpInverted(cmd: UInt) = cmd(0)
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def cmpEq(cmd: UInt) = !cmd(3)
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}
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import ALU._
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import Instructions._
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class ALU(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, xLen)
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val in1 = UInt(INPUT, xLen)
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val out = UInt(OUTPUT, xLen)
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val adder_out = UInt(OUTPUT, xLen)
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val cmp_out = Bool(OUTPUT)
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}
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// ADD, SUB
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val in2_inv = Mux(isSub(io.fn), ~io.in2, io.in2)
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val in1_xor_in2 = io.in1 ^ in2_inv
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io.adder_out := io.in1 + in2_inv + isSub(io.fn)
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// SLT, SLTU
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val slt =
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Mux(io.in1(xLen-1) === io.in2(xLen-1), io.adder_out(xLen-1),
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Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1)))
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io.cmp_out := cmpInverted(io.fn) ^ Mux(cmpEq(io.fn), in1_xor_in2 === UInt(0), slt)
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// SLL, SRL, SRA
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val (shamt, shin_r) =
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if (xLen == 32) (io.in2(4,0), io.in1)
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else {
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require(xLen == 64)
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val shin_hi_32 = Fill(32, isSub(io.fn) && io.in1(31))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0))
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(shamt, Cat(shin_hi, io.in1(31,0)))
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}
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val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
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val shout_r = (Cat(isSub(io.fn) & shin(xLen-1), shin).asSInt >> shamt)(xLen-1,0)
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val shout_l = Reverse(shout_r)
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val shout = Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r, UInt(0)) |
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Mux(io.fn === FN_SL, shout_l, UInt(0))
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// AND, OR, XOR
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val logic = Mux(io.fn === FN_XOR || io.fn === FN_OR, in1_xor_in2, UInt(0)) |
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Mux(io.fn === FN_OR || io.fn === FN_AND, io.in1 & io.in2, UInt(0))
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val shift_logic = (isCmp(io.fn) && slt) | logic | shout
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val out = Mux(io.fn === FN_ADD || io.fn === FN_SUB, io.adder_out, shift_logic)
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io.out := out
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if (xLen > 32) {
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require(xLen == 64)
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when (io.dw === DW_32) { io.out := Cat(Fill(32, out(31)), out(31,0)) }
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}
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}
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