107 lines
3.3 KiB
Scala
107 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import freechips.rocketchip.config.Parameters
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class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
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val size = typ(log2Up(log2Up(maxSize)+1)-1,0)
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def misaligned =
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(addr & ((UInt(1) << size) - UInt(1))(log2Up(maxSize)-1,0)).orR
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def mask = {
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var res = UInt(1)
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for (i <- 0 until log2Up(maxSize)) {
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val upper = Mux(addr(i), res, UInt(0)) | Mux(size >= UInt(i+1), UInt((BigInt(1) << (1 << i))-1), UInt(0))
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val lower = Mux(addr(i), UInt(0), res)
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res = Cat(upper, lower)
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}
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res
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}
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protected def genData(i: Int): UInt =
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if (i >= log2Up(maxSize)) dat
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else Mux(size === UInt(i), Fill(1 << (log2Up(maxSize)-i), dat((8 << i)-1,0)), genData(i+1))
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def data = genData(0)
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def wordData = genData(2)
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}
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class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
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private val size = new StoreGen(typ, addr, dat, maxSize).size
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private def genData(logMinSize: Int): UInt = {
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var res = dat
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for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
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val pos = 8 << i
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val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
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val doZero = Bool(i == 0) && zero
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val zeroed = Mux(doZero, UInt(0), shifted)
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res = Cat(Mux(size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
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}
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res
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}
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def wordData = genData(2)
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def data = genData(0)
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}
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class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
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require(operandBits == 32 || operandBits == 64)
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val io = new Bundle {
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val mask = UInt(INPUT, operandBits/8)
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val cmd = Bits(INPUT, M_SZ)
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val lhs = Bits(INPUT, operandBits)
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val rhs = Bits(INPUT, operandBits)
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val out = Bits(OUTPUT, operandBits)
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}
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val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
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val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
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val add = io.cmd === M_XA_ADD
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val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
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val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
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val adder_out =
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if (operandBits == 32) io.lhs + io.rhs
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else {
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val mask = ~UInt(0,64) ^ (!io.mask(3) << 31)
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(io.lhs & mask) + (io.rhs & mask)
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}
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val less = {
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val sgned = {
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val mask = M_XA_MIN ^ M_XA_MINU
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(io.cmd & mask) === (M_XA_MIN & mask)
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}
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if (operandBits == 32) {
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Mux(io.lhs(31) === io.rhs(31), io.lhs < io.rhs, Mux(sgned, io.lhs(31), io.rhs(31)))
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} else {
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val cmp_lhs = Mux(!io.mask(4), io.lhs(31), io.lhs(63))
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val cmp_rhs = Mux(!io.mask(4), io.rhs(31), io.rhs(63))
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val lt_lo = io.lhs(31,0) < io.rhs(31,0)
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val lt_hi = io.lhs(63,32) < io.rhs(63,32)
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val eq_hi = io.lhs(63,32) === io.rhs(63,32)
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val lt =
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Mux(io.mask(4) && io.mask(3), lt_hi || eq_hi && lt_lo,
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Mux(io.mask(4), lt_hi, lt_lo))
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Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
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}
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}
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val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
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val logic =
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Mux(logic_and, io.lhs & io.rhs, 0.U) |
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Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
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val out =
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Mux(add, adder_out,
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Mux(logic_and || logic_xor, logic,
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minmax))
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val wmask = FillInterleaved(8, io.mask)
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io.out := wmask & out | ~wmask & io.lhs
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}
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