97 lines
3.0 KiB
Scala
97 lines
3.0 KiB
Scala
// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.rocket.constants
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import Chisel._
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import freechips.rocketchip.util._
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import scala.math._
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trait ScalarOpConstants {
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val MT_SZ = 3
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def MT_X = BitPat("b???")
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def MT_B = UInt("b000")
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def MT_H = UInt("b001")
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def MT_W = UInt("b010")
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def MT_D = UInt("b011")
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def MT_BU = UInt("b100")
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def MT_HU = UInt("b101")
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def MT_WU = UInt("b110")
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def mtSize(mt: UInt) = mt(MT_SZ-2, 0)
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def mtSigned(mt: UInt) = !mt(MT_SZ-1)
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val SZ_BR = 3
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def BR_X = BitPat("b???")
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def BR_EQ = UInt(0, 3)
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def BR_NE = UInt(1, 3)
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def BR_J = UInt(2, 3)
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def BR_N = UInt(3, 3)
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def BR_LT = UInt(4, 3)
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def BR_GE = UInt(5, 3)
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def BR_LTU = UInt(6, 3)
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def BR_GEU = UInt(7, 3)
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def A1_X = BitPat("b??")
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def A1_ZERO = UInt(0, 2)
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def A1_RS1 = UInt(1, 2)
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def A1_PC = UInt(2, 2)
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def IMM_X = BitPat("b???")
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def IMM_S = UInt(0, 3)
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def IMM_SB = UInt(1, 3)
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def IMM_U = UInt(2, 3)
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def IMM_UJ = UInt(3, 3)
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def IMM_I = UInt(4, 3)
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def IMM_Z = UInt(5, 3)
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def A2_X = BitPat("b??")
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def A2_ZERO = UInt(0, 2)
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def A2_SIZE = UInt(1, 2)
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def A2_RS2 = UInt(2, 2)
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def A2_IMM = UInt(3, 2)
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def X = BitPat("b?")
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def N = BitPat("b0")
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def Y = BitPat("b1")
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val SZ_DW = 1
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def DW_X = X
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def DW_32 = Bool(false)
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def DW_64 = Bool(true)
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def DW_XPR = DW_64
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}
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trait MemoryOpConstants {
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val NUM_XA_OPS = 9
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val M_SZ = 5
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def M_X = BitPat("b?????");
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def M_XRD = UInt("b00000"); // int load
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def M_XWR = UInt("b00001"); // int store
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def M_PFR = UInt("b00010"); // prefetch with intent to read
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def M_PFW = UInt("b00011"); // prefetch with intent to write
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def M_XA_SWAP = UInt("b00100");
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def M_FLUSH_ALL = UInt("b00101") // flush all lines
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def M_XLR = UInt("b00110");
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def M_XSC = UInt("b00111");
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def M_XA_ADD = UInt("b01000");
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def M_XA_XOR = UInt("b01001");
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def M_XA_OR = UInt("b01010");
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def M_XA_AND = UInt("b01011");
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def M_XA_MIN = UInt("b01100");
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def M_XA_MAX = UInt("b01101");
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def M_XA_MINU = UInt("b01110");
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def M_XA_MAXU = UInt("b01111");
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def M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
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def M_PWR = UInt("b10001") // partial (masked) store
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def M_PRODUCE = UInt("b10010") // write back dirty data and cede W permissions
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def M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
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def M_SFENCE = UInt("b10100") // flush TLB
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def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
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def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
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def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
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def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
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def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
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def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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}
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