Andrew Waterman
fdd19145e9
bump chisel/hardfloat/junctions/uncore submodules
2016-01-17 01:50:04 -08:00
Howard Mao
04fd407c3e
bump rocket submodule pointer
2016-01-15 15:29:23 -08:00
Howard Mao
3b4b7126ed
Chisel3 compile-time deprecations should be runtime errors
2016-01-14 15:12:41 -08:00
Howard Mao
33aa64212d
fix more Chisel3 deprecations
2016-01-14 15:06:30 -08:00
Andrew Waterman
fc638c6339
Chisel3 compatibility fixes
2016-01-12 16:28:05 -08:00
Andrew Waterman
603db5e271
Chisel3 compatibility; new NaNs; new MIPI behavior
2016-01-12 16:25:03 -08:00
Howard Mao
c06884b78c
lowercase SMI to Smi
2016-01-11 17:44:10 -08:00
Colin Schmidt
8d1afa4197
bump fpga repo
2016-01-09 17:50:29 -08:00
Howard Mao
806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
Howard Mao
2f71a3da5a
bump up submodule commits to merge commits
...
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
2015-12-22 08:09:24 -08:00
Howard Mao
0f51ca4c10
Merge pull request #35 from ucb-bar/dma
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Implement DMA unit
2015-12-22 10:33:59 -05:00
Howard Mao
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
Colin Schmidt
c080e82e92
Merge pull request #34 from seldridge/rocketchip-addons-build
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build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 11:57:19 -08:00
Schuyler Eldridge
e50e4d4c84
build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 14:17:16 -05:00
Andrew Waterman
91be080526
Merge pull request #32 from ucb-bar/javamaxpermsize
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Double Java MaxPermSize.
2015-12-07 13:58:41 -08:00
Jim Lawson
c5e9558571
Double Java MaxPermSize.
2015-12-07 12:05:06 -08:00
Howard Mao
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
Howard Mao
6fc1e92708
add option to print cycle count regardless of exit status
2015-12-04 12:04:13 -08:00
Howard Mao
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
Howard Mao
ebf2417a32
rocc-fpu-port merged into master for rocket
2015-12-02 09:02:43 -08:00
Howard Mao
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
Andrew Waterman
5eeb8969f6
fix zscale build (run still fails)
2015-12-01 16:20:34 -08:00
Howard Mao
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
Howard Mao
e4043570bd
bump groundtest and hardfloat
2015-11-30 18:06:15 -08:00
Howard Mao
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
Colin Schmidt
ec4ade988b
[travis] add multiple configs including rocc
2015-11-28 07:17:49 -08:00
Colin Schmidt
7259239ba4
Merge pull request #31 from ucb-bar/multirocc
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implement support for multiple RoCC accelerators
2015-11-28 08:56:07 -05:00
Howard Mao
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60
Construct device tree ROM in MMIO region
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Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
Andrew Waterman
49d93da87e
Factor out more common zscale code
2015-11-24 19:17:21 -08:00
Andrew Waterman
52b25c3da0
Factor out more common zscale code
2015-11-24 18:34:03 -08:00
Andrew Waterman
1761db3272
Factor out some common code from zscale
2015-11-24 18:14:06 -08:00
Howard Mao
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
Yunsup Lee
ea8ba49805
improve memory system: specialize MultiChannel routing
2015-11-18 21:58:22 -08:00
Andrew Waterman
5195a5b891
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
Henry Cook
485f1b7bd7
bump uncore
2015-11-16 18:14:03 -08:00
Yunsup Lee
8916c7e99c
push rocket
2015-11-14 16:43:28 -08:00
Yunsup Lee
6a6371fdb6
move to new version of hardfloat
2015-11-14 14:50:13 -08:00
Howard Mao
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
Colin Schmidt
97d0e195ae
Merge pull request #28 from ucb-bar/yusnup
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Don't re-generate the .d files on "make clean"
2015-11-12 00:46:21 -08:00
