riscv/rocket-chip
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3334 Commits

Author SHA1 Message Date
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Howard Mao
8550582f84 remove redundant verilator rule 2016-09-14 20:31:17 -07:00
jackkoenig
a304695ffd Add firrtl and verilog Makefile targets to vsim 2016-09-14 20:29:59 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes .
 2016-09-14 20:06:22 -07:00
Yunsup Lee
96110caca1 Merge pull request from ucb-bar/move-bootrom 
Move BootROM from Coreplex to Periphery
 2016-09-14 19:51:16 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Yunsup Lee
f2cb9da91a Merge pull request from ucb-bar/split-unittest 
refactor unittest framework
 2016-09-14 18:56:11 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
mwachs5
ae026edeb3 Merge pull request from ucb-bar/async_clk_utils 
Add some async/clock utilities
 2016-09-14 16:59:27 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Scott Beamer
f7121a2a5b support for BSD sed (GNU sed still works) 2016-09-14 12:21:39 -07:00
Scott Beamer
cd12fd1cbb fix clang support for emulator-debug 2016-09-14 12:20:37 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman
2572cd3f7c Add missing dependency 2016-09-14 11:50:28 -07:00
Andrew Waterman
5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
Andrew Waterman
38b13da2f4 Bump chisel and firrtl 2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written () 2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao
1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
dfd6bfb454 Merge pull request from ucb-bar/crossing-take-2 
Clock crossing redux
 2016-09-13 19:13:21 -07:00
Wesley W. Terpstra
d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case () 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook
28982ab569 Merge pull request from ucb-bar/monitor 
TL2 Monitor and Fuzzer
 2016-09-13 14:04:23 -07:00
Henry Cook
632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
roman3017
2979badf75 Update README.md 
Fixed path to Configs.scala
 2016-09-12 18:55:14 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Colin Schmidt
a10d058e1a fix warnings in verilog source () 2016-09-12 18:25:35 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00