riscv/rocket-chip
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f2d4cb8152
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226 Commits

Author SHA1 Message Date
Andrew Waterman
f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew Waterman
c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew Waterman
d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Megan Wachs
c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Andrew Waterman
67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory 2017-04-20 08:47:03 -07:00
Andrew Waterman
d82a0dc231 Mitigate D$ exception critical path, yet again 2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d Only report D$ exceptions on not-nacked accesses 2017-04-18 00:47:58 -07:00
Andrew Waterman
a956b78dd2 In TLBPermissions, merge across some region types 
We only care whether they have side effects or not.
 2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894 Pipeline D$ exception response into s2 2017-04-18 00:47:58 -07:00
Andrew Waterman
cc9ec1d51a Send D$ grant acks early; accept release acks early 
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
 2017-04-18 00:47:58 -07:00
Andrew Waterman
728569c717 Reduce access-exception generation critical path 2017-04-18 00:47:58 -07:00
Andrew Waterman
c366007a0d Tighten PMAs for LR/SC and misaligned accesses 
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
 2017-04-18 00:47:58 -07:00
Andrew Waterman
74a7838de0 In TLBPermissions, don't merge regions of different types 2017-04-18 00:47:58 -07:00
Andrew Waterman
7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew Waterman
debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew Waterman
a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Andrew Waterman
fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) 
* only replicate scratch slave d-channel resp when AMO req

* dtim: port can't support put partial mask with holes

* dtim: use \!isRead instead of isAMO

* Fix ScratchpadSlavePort looking at wrong Acquire message

Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
 2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf Unconditionally write badaddr, possibly to zero 
59d33f6b83
 2017-04-12 13:35:02 -07:00
Andrew Waterman
470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew Waterman
a43bf2feae Add vectored interrupt support 
4dcaa944ba

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

ba6d88466a
 2017-04-08 00:29:45 -07:00
Andrew Waterman
c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
solomatnikov
127f121ef2 Preserve id_do_fence (#651) 2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Andrew Waterman
410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Henry Cook
b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Andrew Waterman
a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Megan Wachs
bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00