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Commit Graph

3678 Commits

Author SHA1 Message Date
9ea8c4e781 Add an 8-channel backup memory port config
Now that the backup memory port works I want to test it.
2016-02-27 10:56:13 -08:00
7319f430d0 Fix the backup memory port on multiple-channel configs
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
2016-02-27 10:47:52 -08:00
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
68a49c7700 fetch rocketchip_addons during regression submodule step 2016-02-26 11:05:41 -08:00
8c73d10fe1 Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
ebffd69b8e Provide both __OFFSET and __PADDR for SCR entries
This was recently changed to write out physical addresses for SCR file entries,
but to bring up the chip we need SCR offsets so we can write the uncore SCR
file over HTIF.  This changes the map generator to generate both.

Without this change things happened to work anyway because the high bits were
getting dropped by the SCR file.
2016-02-25 21:48:32 -08:00
640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring
RoCC PTW refactoring
2016-02-25 18:01:01 -08:00
091782ad27 Merge pull request #29 from ucb-bar/rocc-ptw-refactoring
RoCC PTW refactoring
2016-02-25 17:57:22 -08:00
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
15ac4d317f RoCC PTW refactoring 2016-02-25 17:15:38 -08:00
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
19420cd5df add utility overloads of SCRIO.attach, pass base address so that generated c header is correct, and print debug messages/header in hex instead of decimal 2016-02-24 15:26:55 -08:00
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
90a73c621d Merge pull request #58 from ucb-bar/more-travis-fixing
More travis fixing
2016-02-23 21:26:16 -08:00
58d6af207f Cache all the Scala build directories
I hope this will result in Travis building our stuff a lot faster, since this
currently takes about half the time.
2016-02-23 16:47:48 -08:00
4f5b1da58b add a resp_len helper to AtosRequest 2016-02-23 16:24:32 -08:00
db3b2c264c Add constructors, converters, and serdes for AXI tunneled over SERDES (AtoS) 2016-02-23 16:24:32 -08:00
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
8873222e42 fix cache release assertion 2016-02-23 16:03:51 -08:00
ad62afd9ca Add zscale to regression submodule list 2016-02-23 12:58:08 -08:00
700d756de0 Merge pull request #55 from ucb-bar/travis-regression
travis-ci.org improvements
2016-02-23 12:19:59 -08:00
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/...
This uses the compiled tests in RISCV, which match the rest of the toolchain.
2016-02-23 10:58:51 -08:00
1e49eb4958 format .travis.yml (trigger rebuilt to test cache) 2016-02-23 10:58:51 -08:00
e097cdcef8 bump tools for install tests fix 2016-02-23 10:58:51 -08:00
28c91795c3 Enable travis caching 2016-02-23 10:58:51 -08:00
edd0b3b824 Move travis to the regression Makefile
We want to add support for caching riscv-tools builds on Travis and the easiest
way to do so looks like to jus go ahead and use
2016-02-23 10:58:51 -08:00
c2e9971b5f move toaxe.py script into top-level Rocket-Chip repo 2016-02-23 08:52:32 -08:00
1b6871f3d8 Add author, affiliation, and sponsor info to trace-generator files. 2016-02-23 15:30:11 +00:00
0ac5c07683 Merge pull request #54 from ucb-bar/fsim-no-htif
The FPGA doesn't have an HTIF clock divider
2016-02-22 20:02:03 -08:00
a073c37e36 The FPGA doesn't have an HTIF clock divider
We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.
2016-02-22 16:15:07 -08:00
c1b5f71ee7 don't run bmarks in parallel 2016-02-22 13:34:24 -08:00
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
91e3c9b96f reuse generator parameters for tracegen 2016-02-22 09:53:31 -08:00
43c2237ef7 add more memtest configs and remove channel test 2016-02-22 09:38:44 -08:00
0c575403af only use a single asm test and 1 bmark for memtest 2016-02-22 09:36:53 -08:00
e4c4a90648 add a config to travis for memchannel mux select 2016-02-22 09:36:53 -08:00
3dae576c9e add travis configs for memtest 2016-02-22 09:36:53 -08:00
e63fc3bb44 Added trace generator 2016-02-22 08:43:34 -08:00
4fedd180ee bump uncore and groundtest 2016-02-19 23:31:09 -08:00
da302504a5 get rid of sequential same id get regression in broadcast regression suite 2016-02-19 23:14:34 -08:00
85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
000af5e662 add NastiIOHostIO converter test 2016-02-19 11:21:53 -08:00
f97bd70df5 add NastiIO to HostIO converter 2016-02-19 11:21:23 -08:00
fbd66ac87b expose a count in MultiWidthFifo 2016-02-19 11:20:43 -08:00
5241ee6442 add multi-width FIFO 2016-02-19 11:20:43 -08:00