riscv/rocket-chip
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262 Commits

Author SHA1 Message Date
mwachs5 a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Andrew Waterman a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Wesley W. Terpstra dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra 0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra 9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Jack Koenig f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
Henry Cook 0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
Howard Mao 49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao 646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Henry Cook cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Wesley W. Terpstra 1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Henry Cook 1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Megan Wachs 1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Henry Cook aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman 5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
mwachs5 47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) 2016-09-14 00:17:26 -07:00
Howard Mao bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao 1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra 44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra 33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook 632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Wesley W. Terpstra 606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra 7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra 273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra 9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra 42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra 94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook 0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00