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Commit Graph

3504 Commits

Author SHA1 Message Date
Scott Johnson
2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
Scott Johnson
4dbcc568dc reorder code to get rid of messy -1 2016-08-19 16:55:57 -07:00
Scott Johnson
f945acf712 rm race condition on trace_count 2016-08-19 16:55:57 -07:00
Megan Wachs
75efc7dee7 JtagIO's DRV_TDO should be an INPUT 2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb Move files after the file reorganization 2016-08-19 16:11:41 -07:00
Megan Wachs
48c5ec3551 add missing jtag file 2016-08-19 16:08:32 -07:00
Megan Wachs
66a253a0db Remove unncessary file 2016-08-19 16:08:31 -07:00
Megan Wachs
3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module.
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0
2016-08-19 16:08:31 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
ceff6dd0c8 update README 2016-08-19 13:45:23 -07:00
Howard Mao
40bd87bce4 cache the verilator install in travis 2016-08-19 13:45:23 -07:00
Howard Mao
1c5034707b fix submodules in regression makefile 2016-08-19 13:45:23 -07:00
Howard Mao
f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
Howard Mao
eba692786b make sure FIRRTL jar gets updated timestamp 2016-08-19 13:45:23 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Howard Mao
f78da0b0ea add required cloneType methods in non-blocking L1 2016-08-19 13:44:53 -07:00
Andrew Waterman
114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
Andrew Waterman
3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
2016-08-19 12:06:17 -07:00
Andrew Waterman
fee5d2b1ea Remove parameters for some things that aren't parameterizable
Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
2016-08-19 12:04:13 -07:00
Howard Mao
33676e81f8 use isOneOf as much as possible 2016-08-19 09:56:06 -07:00
Howard Mao
d34e790ac0 get rid of duplicated code in rocket Util 2016-08-18 18:40:07 -07:00
Howard Mao
7671811ac9 merge uncore.Util into uncore.util 2016-08-18 18:33:46 -07:00
Colin Schmidt
0a6c05a5d8 connect top level interrupts to coreplex 2016-08-18 15:52:44 -07:00
Howard Mao
91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao
1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao
18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao
f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao
d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
David Biancolin
de316643d1 Merge pull request #205 from ucb-bar/configurable_memsize
make memsize configurable
2016-08-17 18:33:56 -07:00
David Biancolin
29600f64ec make memsize configurable 2016-08-17 16:31:34 -07:00
Andrew Waterman
5164f947c0 Validate mstatus.mpp/dcsr.prv values on MRET/DRET
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
2016-08-17 15:39:34 -07:00
Howard Mao
35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Andrew Waterman
2d1d7266f5 Fix RV64 badaddr value on instruction faults with large addresses
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
2016-08-15 23:09:09 -07:00
Howard Mao
38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) 2016-08-15 23:08:55 -07:00
Howard Mao
47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao
a756856d84 make sure coreplex sources included in make dependencies 2016-08-11 14:27:03 -07:00
Howard Mao
e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao
163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Howard Mao
4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao
571d579b86 get unit tests working again 2016-08-10 11:23:07 -07:00
Howard Mao
0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00