Howard Mao
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4c3c3c630e
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add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len
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2015-09-10 17:55:10 -07:00 |
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Christopher Celio
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17e971bbfa
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Add emulator "make debug" and "-j" to travis
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2015-09-10 17:34:16 -07:00 |
|
Howard Mao
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6387d31c62
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add comments and small fixes for NASTI and SMI
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2015-09-10 17:33:48 -07:00 |
|
Howard Mao
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8a8d52da4f
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add convenient constructors for NASTI channels
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2015-09-10 17:33:31 -07:00 |
|
Christopher Celio
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d9a2162472
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Bump Chisel
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2015-09-10 17:26:41 -07:00 |
|
Christopher Celio
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8f71c4da2d
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Reintroduced multiple emulator backend directories
Fixes a "make -j" concurrency bug due to deleting files that another
parallel rule depends on.
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2015-09-10 17:14:23 -07:00 |
|
Christopher Celio
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83df4bcc35
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Fixed run-bmark-tests make target in vsim
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2015-09-09 22:37:47 -07:00 |
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Colin Schmidt
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af7336ef8b
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blacklist private branches from travis
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2015-09-08 15:13:38 -07:00 |
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Colin Schmidt
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d292b6cb13
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don't connect rocc-fpu-port without rocc accel
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2015-09-08 14:44:12 -07:00 |
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Andrew Waterman
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d08b75c472
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Merge pull request #15 from ucb-bar/fix_disasm_garbage
If you don't have spike-disasm in your path, your path is dumped
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2015-09-03 17:55:31 -07:00 |
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Ben Keller
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8e9c15c10d
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If you don't have spike-disasm in your path, your path is dumped
to stdout by this line every time you do anything in the entire repo.
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2015-09-03 15:36:11 -07:00 |
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Christopher Celio
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e6b6ff5a1d
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Update README.md
Corrected PublicConfigs.scala -> Configs.scala
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2015-09-02 22:55:53 -07:00 |
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Howard Mao
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ede1ada053
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Add converters and utilities for simpler peripheral interface (SMI)
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2015-09-01 14:00:45 -07:00 |
|
Howard Mao
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75ec7529af
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implement NASTI Interconnect generating from configuration address map
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2015-09-01 14:00:45 -07:00 |
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Howard Mao
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b046c57284
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make NASTI -> MemIO converter compliant to AXI4 spec
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2015-09-01 11:17:38 -07:00 |
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Colin Schmidt
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1bfd873888
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bump chisel version for seqmem setname
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2015-08-29 12:53:57 -07:00 |
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Andrew Waterman
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350d530766
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Use Vec.fill, not Vec.apply, for Vec literals
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2015-08-27 10:00:43 -07:00 |
|
Andrew Waterman
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94287fed90
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Avoid type-unsafe assignments
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2015-08-27 09:57:36 -07:00 |
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Andrew Waterman
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05d311c517
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Use Vec.apply, not Vec.fill, for type nodes
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2015-08-27 09:47:02 -07:00 |
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Andrew Waterman
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f7d9628de2
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Avoid needless use of Vec
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2015-08-27 09:40:52 -07:00 |
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Andrew Waterman
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3a1dad7994
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Use Vec.apply, not Vec.fill, for type nodes
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2015-08-27 09:40:24 -07:00 |
|
Iori YONEJI
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0ac6172525
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Add "-memsize" flag to emulator
- Allow user to set memory size (in MiB) used by emulator.
- if memory is exhausted, warn user about memory shortage.
Close #3
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2015-08-26 17:53:37 -07:00 |
|
Christopher Celio
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b55765f597
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Bump riscv-tools
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2015-08-26 16:08:45 -07:00 |
|
Christopher Celio
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b1e845f370
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Add space to README.md
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2015-08-26 14:34:22 -07:00 |
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Scott Beamer
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b88c283b21
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add travis support and tests
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2015-08-25 13:29:20 -07:00 |
|
Scott Beamer
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333c594d2a
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respect environment's CXX
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2015-08-25 13:26:14 -07:00 |
|
Scott Beamer
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49ff021518
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bump fpga repo
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2015-08-21 15:39:59 -07:00 |
|
Albert Ou
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3d6a060dc3
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Bump Scala to 2.11.6
This change, originally part of commit b978083, was excluded from the
merge at commit 47494ec.
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2015-08-10 23:52:58 -07:00 |
|
Henry Cook
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bcf95b39e0
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bump uncore
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2015-08-10 20:08:50 -07:00 |
|
Henry Cook
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005752e2a6
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use the parameters used to create the original object
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2015-08-10 14:43:17 -07:00 |
|
Colin Schmidt
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cab12635f8
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Merge master into rocc-fpu-port
ebb33f2f4b658211960a4c6c023c139420c67212
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2015-08-06 08:03:10 -07:00 |
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Andrew Waterman
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01fc61ba96
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Don't construct so many Vecs
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2015-08-05 18:43:59 -07:00 |
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Howard Mao
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a551a12d70
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add missing Wire wrap in BasicCrossbar
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2015-08-05 17:05:31 -07:00 |
|
Henry Cook
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a3c9431ee2
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bump all submodules for scala version
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2015-08-05 16:50:38 -07:00 |
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Andrew Waterman
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eb6583d607
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use cloneType in PhysicalNetworkIO
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2015-08-05 16:47:49 -07:00 |
|
Andrew Waterman
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9b038db34a
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Upgrade scala to 2.11.6
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2015-08-05 15:37:03 -07:00 |
|
Andrew Waterman
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700910adff
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Chisel3 compatibility fix for <>
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2015-08-05 15:34:40 -07:00 |
|
Andrew Waterman
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1718333f83
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Don't use Vec as lvalue
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2015-08-05 15:29:33 -07:00 |
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Andrew Waterman
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546205b174
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-05 15:29:03 -07:00 |
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Andrew Waterman
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798ddeb5f5
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Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
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2015-08-04 13:15:17 -07:00 |
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Andrew Waterman
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2ff2b43c2c
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Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
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2015-08-04 13:13:44 -07:00 |
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Andrew Waterman
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e469785f5e
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bump scala to 2.11.6
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2015-08-03 19:51:17 -07:00 |
|
Andrew Waterman
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fb5524372d
|
bump scala to 2.11.6
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2015-08-03 19:51:08 -07:00 |
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Andrew Waterman
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fb718f03c1
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bump scala to 2.11.6
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2015-08-03 19:50:58 -07:00 |
|
Andrew Waterman
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d85c46bc60
|
Chisel3 bulk connect non-commutativity
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2015-08-03 19:47:16 -07:00 |
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Andrew Waterman
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d4c94c6566
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Chisel3 has different Vec semantics
Vec(a, b) := c doesn't modify a and b in chisel3.
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2015-08-03 19:08:00 -07:00 |
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Andrew Waterman
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34b9a7fdc5
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Various Chisel3 compatibility changes
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2015-08-03 18:54:56 -07:00 |
|
Andrew Waterman
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77cf26aeba
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Chisel3: Flip order of := and <>
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2015-08-03 18:53:39 -07:00 |
|
Andrew Waterman
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c345d72af4
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Chisel3: Flip order of := and <>
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2015-08-03 18:53:09 -07:00 |
|
Andrew Waterman
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121e4fb511
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Flip direction of some bulk connects
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2015-08-03 18:01:14 -07:00 |
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