Wesley W. Terpstra
adf5f1807b
tilelink2: ToAXI4 bridge added
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
2f7081aeaf
tilelink2: make mask generation reusable
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00
Henry Cook
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
Wesley W. Terpstra
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
Albert Ou
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
Andrew Waterman
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
Jacob Chang
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
...
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303
tilelink2: Nodes should accept full PortParameters
...
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
...
AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
...
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
...
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
Megan Wachs
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
...
* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
...
This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Megan Wachs
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
Henry Cook
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e
[tilelink2] Add unit tests for many TL2 components
...
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
mwachs5
f9e0a7ac24
Merge branch 'master' into async_register_crossing
2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
eaea138d0d
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab
Merge branch 'master' into async_register_crossing
2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c
tilelink2 WidthWidget: Gets must have their mask adjusted ( #353 )
...
The mask of a Get should also be converted.
This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
2016-09-27 13:36:28 -07:00
Howard Mao
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
Wesley W. Terpstra
d9e209365d
Tl2 addr width0 ( #346 )
...
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}
* tilelink2: use addr_lo instead of relying on truncation
Truncation can mess up if the width should be 0, but IS 1.
2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f
tilelink2 AddressSet: add .misaligned(low, size) helper method ( #345 )
...
This helps devices with misaligned ranges still connect to TL2.
2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
1773eb4405
tilelink2 LazyModule: output GraphML of the bus
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc
tilelink2 Nodes: expose connectivity in RootNode
2016-09-26 14:35:46 -07:00
mwachs5
77a0f76289
Cleanup jtag dtm ( #342 )
...
* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
Wesley W. Terpstra
d787bae0d0
tilelink2 Xbar: decouple ready from valid ( #338 )
...
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
d175bb314d
Periphery: make bus width and arithmetic atomics configurable ( #337 )
2016-09-23 15:25:58 -07:00
Wesley W. Terpstra
47843d8ec1
tilelink2: maxLgSize should be accurate ( #332 )
2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11
RegField: remove obsolete split method
...
This is now natively supported by the regmap(...) invocation.
2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10
RegField: add name and description fields
...
In the future we can generate interesting documentation and headers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee
RegMapper: regmap(...) now takes BYTE addresses
...
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.
This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729
RegField: remove RegField.bytes; it was dangerous
...
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
...
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.
For example, this:
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
Henry Cook
391be8d740
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a
tilelink2 Atomics: optimize the sign-extension circuit
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef
tilelink2 Fuzzer: work around for firrtl/verilator performance issue
...
Big Vec()s cause very slow compilation.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc
tilelink2 Monitor: work around for firrtl/verilator performance issue
...
Big Vec()s cause problems for these tools.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb
tilelink2 Atomics: support arithmetic atomics
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51
tilelink2 Atomics: support Logical AMOs
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f
tilelink2 RAMModel: exploit latency to remove bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9
tilelink2 Atomics: exploit minLatency to eliminate bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223
tilelink2 Monitor: detect minLatency violations
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4
tilelink2: most adapters can wipe away latency
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624
tilelink2 Buffer: increase the minLatency on ports
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4
tilelink2: specify the minLatency for SRAM+RR
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3
tilelink2 Parameters: include a minLatency parameter for optimization
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e
tilelink2 Fuzzer: test Atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d
tilelink2 RAMModel: support (by ignoring) atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a
tilelink2 AtomicAutomata: prototype flow control complete
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa
tilelink2: add a general-purpose Arbiter
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8
tilelink2 Fuzzer: only generate legal atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8
tilelink2 Parameters: poison ports with unsafe atomics
...
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f
tilelink2 Nodes: split connect into eager and lazy halves
2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f
tilelink2 Monitor: make it a LazyModule in the hierarchy
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b
tilelink2 Bundles: add 1-way snoop bundles
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f
tilelink2 Monitor: detect if sources are mishandled
2016-09-22 15:14:19 -07:00
Albert Ou
d76b762657
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
...
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Henry Cook
335e866176
[unittest] Parallelize UnitTestSuite ( #319 )
...
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.
* [util] Timer spacing cleanup
* [unittest] Remove Config reference to UnitTestTimeout
2016-09-21 13:05:22 -07:00
Andrew Waterman
12d0c00822
Fix mtime RegField handling
...
RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking. Avoid RegField.bytes by splitting mtime into
a Seq of words.
2016-09-20 15:00:52 -07:00
Wesley W. Terpstra
9817a00ed9
tilelink2: Fuzzer should check address validity before injection
2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1
tilelink2: differentiate fast/safe address lookup cases
2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214
tilelink2: minimize Xbar decode logic
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c
tilelink2: consider the implications of negative address mask
2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548
tilelink2: track interrupt connectivity like in TL2
2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
6c3269a1d8
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
e749558190
ROM: optionally (default: true) executable
2016-09-17 00:19:09 -07:00
Wesley W. Terpstra
8876d83640
Prci: preserve Andrew's preferred clint name
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
a357c1d42e
tilelink2: create DTS for devices automagically
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838
tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1
tilelink2: Nodes can now mix context into parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
dae0918c85
tilelink2 RegisterRouter: support undefZero
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227
tilelink2 RegisterRouterTest: work around firrtl warning
...
Using io.wready leads to verilog that reads from the output...
Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
Port "io_wready" declared as output in module "RRTestCombinational_29" may
need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460
tilelink2 RegisterRouterTest: don't couple fire into helpers
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42
tilelink2 AddressDecoder: validate output of optimization
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122
tilelink2 AddressDecoder: improved heuristic
2016-09-16 16:09:00 -07:00
Andrew Waterman
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d
RegField: separate UInt=>bytes and bytes=>regs
2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d
tilelink2 RegField: .bytes should update more than one byte!
2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4
Fix deprecation warnings
2016-09-16 14:24:19 -07:00
mwachs5
a031686763
util: Do BlackBox Async Set/Reset Registers more properly ( #305 )
...
* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d
Simplify AsyncResetRegVec and make AsyncResetReg companion object
2016-09-16 11:25:10 -07:00
Wesley W. Terpstra
dd19e0911e
tilelink2: handle bus width=1
2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df
PRCI: always use bus width >= XLen
2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
0e80f7fd0f
HintHandler: don't violate Irrevocable rules
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956
RegisterRouter: compress register mapping for sparse devices
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc
tilelink2: compute minimal decisive mask
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3
tilelink2: make RegisterRouter constructor args public
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26
tilelink2: RegField splits up big registers
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32
devices: TL2 version of ROM
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16
tilelink2: Legacy, manager_xact_id does not matter for uncached
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8
tilelink2: add an executable manager parameter
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67
tilelink2: allow := on nodes outside the tilelink2 package
2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
Henry Cook
0a65238920
Merge branch 'master' into tl2-irrevocable
2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
2016-09-14 21:36:27 -07:00
Howard Mao
646527c88e
use named constants to set AXI resp, cache, and prot fields
2016-09-14 21:16:54 -07:00
Henry Cook
cde104b3fa
[junctions] Removes the obsoleted SMI.
...
Closes #280 .
2016-09-14 20:06:22 -07:00
Wesley W. Terpstra
1c7d7f9d32
tilelink2 RegisterRouterTest: stall on both edges
2016-09-14 18:22:12 -07:00
Henry Cook
1b53e477fa
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
2016-09-14 17:43:07 -07:00
Megan Wachs
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
Henry Cook
aa3fa90fe3
[tilelink2] Monitor: miscopied name in assert message
2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab
[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
2016-09-14 14:23:23 -07:00
Andrew Waterman
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b
Give AsyncCrossing slave interfaces registers visibility into when they were written ( #288 )
2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36
move tilelink-agnostic counters from uncore to util package
2016-09-13 20:47:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d
tilelink2: Unit Test for the RegisterCrossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a
tilelink2: unit test for the clock crossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884
tilelink2: add a clock crossing adapter
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8
crossings: change defaults to sync=3 for safer settling time
...
Make the matching AsyncQueue depth=8 to support full throughput
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e
tilelink2: add a RegisterCrossing primitive
2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
ecdfb528c5
crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain
2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db
tilelink2 RAMModel: fix put, get, putAck, getAck case ( #282 )
...
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
2016-09-13 15:44:36 -07:00
Henry Cook
632b5896b9
Delete TestGraphs.scala
...
Re-do later using Fuzzer
2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48
[tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments.
2016-09-13 12:25:57 -07:00
Wesley W. Terpstra
606f19a17f
tilelink2: RegisterRouter Unit Test
2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651
tilelink2 HintHandler: don't HintAck in the middle of a multibeat op
2016-09-12 19:06:35 -07:00
Wesley W. Terpstra
273d3a73f2
tilelink2: Unit Test passes!
2016-09-12 18:39:50 -07:00
Wesley W. Terpstra
9874bc553a
tilelink2: Fragmenter supports Hints
2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490
tilelink2: HintHandler optimize to nothing if unneeded
2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d
tilelink2 HintHandler: fill in correct sink in responses
2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138
tilelink2: Hints are not special
...
Hints have a TransferSize limit just like all other message types.
2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89
[tilelink2] Fuzzer: Rewrite of fuzzer
...
Multiple bug-fixes and actual source id generation.
2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179
[tilelink2] Monitor: Allow zero-mask PutPartials
...
this will require a larger address refactoring TBD
2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86
tilelink2 Fragmenter: bugfix using D.hasData
2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb
[tilelink2] Edges: add size to addr_lo.
...
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
2016-09-12 16:58:09 -07:00
Henry Cook
a21b04a7c1
playground for making different DAGs to use as DUTs
2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637
Initial version of fuzzer and simple ram fuzz test
2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76
tilelink2 RegisterRouter: add RegField test patterns
2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108
tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible
2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c
tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd
tilelink2 Parameters: fix width=1 address truncation bug
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7
tilelink2 RAMModel: clear Mems on power-up
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de
tilelink2 RAMModel: model the state a RAM would have for Put+Gets
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146
tilelink2 Parameters: if you support PutPartial, you must support PutFull
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8
tilelink2 Edge: add a numBeats1 method for predecremented code
2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927
tilelink2 Buffer: support an unlimited number of channels
2016-09-12 10:32:24 -07:00
Megan Wachs
77e4aa63f8
Get rid of the unecessary Parameters for Async Reset Reg
2016-09-09 16:24:35 -07:00
Megan Wachs
5f5989848c
Merge remote-tracking branch 'origin/master' into black_box_regs
2016-09-09 13:12:52 -07:00
Wesley W. Terpstra
c28ca37944
tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
...
We can more reliably find the current LazyModule from the LazyModule.stack
2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3
tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
...
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
2016-09-08 21:34:20 -07:00
Wesley W. Terpstra
48ca478578
Merge branch 'master' into intbar
2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4
tilelink2 Legacy: it's only an error if it's valid ( #264 )
2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76
Add a way to create Async Reset Registers and a way to easily access them with TL2
2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2
tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices
2016-09-08 20:02:07 -07:00
Wesley W. Terpstra
cbf0670156
tilelink2 Legacy: it's only an error if it's valid
2016-09-08 19:32:00 -07:00
Wesley W. Terpstra
1b07d53f70
tilelink2 IntNodes: record interrupt ranges in parameters
2016-09-08 18:51:43 -07:00
Wesley W. Terpstra
66f58cf2d0
tilelink2 RegisterRouter: support new TL2 interrupts
2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d
tilelink2 IntNodes: support interrupt graphs
2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109
tilelink2: connect Nodes to LazyModules for better error messages
2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4
tilelink2 Nodes: support non-Bundle data for io type
2016-09-08 15:19:12 -07:00
Wesley W. Terpstra
60a503dc2f
tilelink2 RegField: add a w1ToClear RegField
2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd
tilelink2 Bundles: fix wrong sink width!
2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5
TL2 WidthWidget ( #258 )
...
* tilelink2 Narrower: support widenening and narrowing on all channels
Be extra careful with the mask transformations
We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.
* tilelink2 SRAM: work around firrtl SeqMem bug
* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)
* tilelink2 mask: fix an issue with width=1 data buses
2016-09-08 10:38:38 -07:00
Andrew Waterman
23d0b31615
Merge branch 'master' into tilelink2.2
2016-09-07 11:47:50 -07:00
Andrew Waterman
02a2439222
Support a degenerate PLIC with no interrupts
...
Resolves #249
2016-09-07 11:21:13 -07:00
Wesley W. Terpstra
d2421654c4
tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
...
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
2016-09-06 23:46:44 -07:00
Wesley W. Terpstra
aae4230627
tilelink2: fix bugs found by Megan in Legacy converter
2016-09-06 13:12:33 -07:00
Wesley W. Terpstra
54ab14cd9d
tilelink2: statically optimize numBeats for simple managers
2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f
tilelink2: stricter TransferSizes requirements
2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c
tilelink2: be more forgiving in what Legacy TL requires
2016-09-05 21:12:51 -07:00
Wesley W. Terpstra
3167539331
tilelink2: Narrower must be little-endian
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
ded246fb95
tilelink2: relax max transfer size; the real requirement is not exceeding alignment
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cf0291061d
tilelink2: fix a bug in UIntToOH1 triggered if the size was too big
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
9f45212c95
tilelink2: Fragmenter needs to update subaddress
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
757d46279e
tilelink2: expand data correctly in D channel narrower
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
0faa8c4051
tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
a0c25880c7
tilelink2: Monitor should check mask of reconstructed request
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
df32cc3887
tilelink2: be careful; apply Andrew's masking trick everywhere
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
fb262558ee
tilelink2: helper objects should pass source line from where they were invoked
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
1a081b4dd5
tilelink2: Monitor should report which TL connection was the problem
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cb54df0a8a
tilelink2: tie off unused channels
2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
68e64a9859
tilelink2: clarify ready-valid use of RegisterRouter
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e3b3543841
tilelink2: ensure RegFields don't exceed their bounds
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
8343070639
tilelink2: detect 1-bit overflow in register definitions
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
a1fc01fd6d
tilelink2: prevent mapping the same register twice
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
81162a2dc9
tilelink2: support attaching a DecoupledIO directly to a register
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
6a378e79e3
tilelink2: allow 0-stage backpressure in combinational regmap
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4746cf00ce
tilelink2: move files to new uncore directory
2016-09-05 20:58:40 -07:00
Howard Mao
a7f79aa409
get rid of TileLinkMemorySelector
2016-09-04 10:55:19 -07:00
Howard Mao
f0ab6d0214
tie off finish signals in tilelink wrapper and unwrapper
2016-09-04 10:55:19 -07:00
Jim Lawson
dc9ae19936
Work-around for current Scala compiler "structural type loses implicits".
...
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.
[error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
[error] possible cause: maybe a semicolon is missing before `value asOutput'?
[error] }.asOutput
[error] ^
[error] one error found
[error] (uncore/compile:compileIncremental) Compilation failed
This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
2016-09-02 15:38:18 -07:00
Andrew Waterman
e23e4d6de5
Add ClientUncachedTileLinkEnqueuer utility
2016-09-02 15:27:54 -07:00
Andrew Waterman
7aeb42fa55
Allow narrow TL interface on PRCI; make mtime writable
2016-09-02 15:27:54 -07:00
Megan Wachs
3dd51ff734
This commit adds Logic & test support for JTAG implementation of Debug Transport Module.
...
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
includes cases where they are used, but because they are not reset asynchronously,
a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
DTM and synchronizer is instantiated within Top, as it is a real piece of
hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.
To build Verilog which includes the JtagDTM within Top:
make CONFIG=WithJtagDTM_...
To test using gdb->OpenOCD->jtag_vpi->Verilog:
First, install openocd (included in this commit)
./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install
Then to run a simulation:
On a 32-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-e300-sim \
SimpleRegisterTest.test_s0
On a 64-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-u500-sim \
SimpleRegisterTest.test_s0
2016-08-19 16:08:31 -07:00
Megan Wachs
dd4a50c452
Add JTAG DTM and test support in simulation
...
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00