3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
9dd12545d0
[Rocket] Send correct type for iomshr reqs
...
Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
5980dc160f
Don't allow multiple entries for same PC in BTB
...
Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
516481b68b
Improve back-to-back integer multiplication performance
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More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
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This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
e0188f8aa4
Don't implicitly fence on CSR instructions
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CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
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The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
5566bf1b13
Don't route PLIC interrupts through PRCI
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The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
