riscv/rocket-chip
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d2da33e4b1
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1151 Commits

Author SHA1 Message Date
Wesley W. Terpstra
d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
Wesley W. Terpstra
43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines 
It's redundant with the new scheme, so just adds HW for no reason.
 2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result 
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
 2017-03-07 20:51:32 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Wesley W. Terpstra
676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
0178248551 diplomacy: evaluate ResourceBindings only once 2017-03-03 02:04:17 -08:00
Wesley W. Terpstra
8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
7660be039c rocketchip: add WithTimebase to set RTC frequency 2017-03-03 00:47:50 -08:00
Wesley W. Terpstra
57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
Wesley W. Terpstra
4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
e322692d16 diplomacy: add DeviceTree renderer 2017-03-02 21:19:14 -08:00
Wesley W. Terpstra
c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet 2017-03-02 11:14:28 -08:00
Wesley W. Terpstra
bb70b1a3c3 diplomacy: add resource tracking 2017-03-02 11:14:28 -08:00
Henry Cook
9bfcb40cb4 util: Majority on sets of bools 2017-02-27 20:18:28 -08:00
Henry Cook
6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments 2017-02-27 19:40:55 -08:00
Henry Cook
62f5727bc6 periphery: peripheryBusBytes and socBusBytes 2017-02-27 19:19:41 -08:00
Andrew Waterman
dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Henry Cook
35877e6ec1 Merge branch 'master' into periphery-adjustments 2017-02-24 10:37:41 -08:00
Leway Colin
87d909e996 Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) 2017-02-24 10:37:26 -08:00
Henry Cook
a281ad8ad2 rocketchip: rename some periphery ports 2017-02-23 18:28:04 -08:00
Henry Cook
6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] 2017-02-23 18:27:44 -08:00
Wesley W. Terpstra
c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Henry Cook
027d6247b6 diplomacy: silence a warning (#560) 2017-02-22 11:28:04 -08:00
Wesley W. Terpstra
9153a9a733 ClockDivider: add docs to appease the reviewer 
... even though this means a delay of 1:30 hours :(
 2017-02-17 19:35:08 +01:00
Wesley W. Terpstra
3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Wesley W. Terpstra
5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) 
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
 2017-02-17 14:26:23 +01:00
Wesley W. Terpstra
924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
bb334a2cf5 util: add fast2slow direction option to rational crossings 
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
 2017-02-17 13:59:51 +01:00
Wesley W. Terpstra
e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. Terpstra
abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00