ClockDivider2: fix launch alignment of clocks (vcs)

Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.

src/main/scala/util/ClockDivider.scala

@@ -5,15 +5,11 @@ package util
 import Chisel._
 
 /** Divide the clock by 2 */
-class ClockDivider2 extends Module {
+class ClockDivider2 extends BlackBox {
   val io = new Bundle {
-    val clock_out = Clock(OUTPUT)
+    val clk_out = Clock(OUTPUT)
+    val clk_in  = Clock(INPUT)
   }
-
-  val clock_reg = Reg(Bool())
-  clock_reg := !clock_reg
-
-  io.clock_out := clock_reg.asClock
 }
 
 /** Divide the clock by power of 2 times.
@@ -30,9 +26,10 @@ class Pow2ClockDivider(pow2: Int) extends Module {
     val dividers = Seq.fill(pow2) { Module(new ClockDivider2) }
 
     dividers.init.zip(dividers.tail).map { case (last, next) =>
-      next.clock := last.io.clock_out
+      next.io.clk_in := last.io.clk_out
     }
 
-    io.clock_out := dividers.last.io.clock_out
+    dividers.head.io.clk_in := clock
+    io.clock_out := dividers.last.io.clk_out
   }
 }