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Commit Graph

5543 Commits

Author SHA1 Message Date
a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
503ce14c98 Merge pull request #307 from ucb-bar/address-shrink
RR: undefined regs return zeros
2016-09-16 16:55:35 -07:00
dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
4abba87b61 bump firrtl to include empty module fix for vivado (#306) 2016-09-16 15:53:53 -07:00
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305)
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
198a2d7022 Merge pull request #302 from ucb-bar/tl2-mmio
Tl2 mmio
2016-09-15 22:45:35 -07:00
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
2c53620275 chisel3: bump for Irrevocable(Decoupled) constructor 2016-09-15 21:28:56 -07:00
0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports 2016-09-15 14:25:47 -07:00
245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor 2016-09-15 13:27:07 -07:00
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
888f6a2a55 Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
2016-09-15 11:48:09 -07:00
29ce599ea2 Merge pull request #295 from ucb-bar/tl2-irrevocable
TL2 -> IrrevocableIO
2016-09-15 11:33:05 -07:00
0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00