Jacob Chang
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
Henry Cook
4234cff074
Merge pull request #444 from ucb-bar/bump-submodules
...
rocketchip: bump all submodules (and remove cde)
2016-11-29 00:13:00 -08:00
Henry Cook
131659cc2a
Merge branch 'master' into bump-submodules
2016-11-28 16:20:42 -08:00
heinzbeinz
d07e30ba97
Update README.md
...
fixed torture link
2016-11-28 16:19:09 -08:00
Henry Cook
a8ee7e0678
Update README
2016-11-28 16:10:50 -08:00
Yunsup Lee
18d100c2b5
Merge pull request #461 from ucb-bar/sifive-copyright
...
Sifive copyright
2016-11-28 15:25:33 -08:00
Henry Cook
86065e5fb8
Merge remote-tracking branch 'origin/master' into bump-submodules
2016-11-28 13:49:59 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
d4708694ea
scripts/authors: Matthew Naylor's submissions were under Berkeley terms
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
8510d9e697
scripts: two scripts to determine copyright holder of files
2016-11-27 22:15:38 -08:00
Wesley W. Terpstra
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
Richard Xia
97a853a995
Merge pull request #459 from ucb-bar/bump-chisel-for-firrtl-jar-gitignore
...
Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
2016-11-26 13:55:53 -08:00
Richard Xia
4e3682f889
Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
2016-11-26 12:24:10 -08:00
Wesley W. Terpstra
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
Wesley W. Terpstra
9433da8458
Merge pull request #457 from ucb-bar/jtag-depth-1
...
Jtag depth 1
2016-11-25 18:41:39 -08:00
Wesley W. Terpstra
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
Wesley W. Terpstra
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
Wesley W. Terpstra
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
Wesley W. Terpstra
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
Colin Schmidt
f19d504c88
Use % in makefrag-verilog to prevent double firrtl execution ( #452 )
...
* Use % in makefrag-verilog to prevent double firrtl execution
2016-11-25 01:50:01 -08:00
Wesley W. Terpstra
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
...
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
Yunsup Lee
549e006988
Merge pull request #451 from ucb-bar/more-configs
...
More configs
2016-11-24 09:44:52 -08:00
Wesley W. Terpstra
6aeadc4551
regression: disable ComparatorL2Config for now
...
This tests atomics against the L2. However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
2016-11-23 20:53:36 -08:00
Wesley W. Terpstra
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
566cc9e60b
rocketchip: RTCPeriod config
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
e87f54d4f7
rocketchip: traits for adding external TL2 ports
2016-11-23 20:44:42 -08:00
Wesley W. Terpstra
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
Henry Cook
76fa62a928
Merge pull request #449 from ucb-bar/post-refactor-cleanup
...
Post refactor cleanup
2016-11-23 13:35:23 -08:00
Henry Cook
837d207064
[travis] split up groundtest into two suites
2016-11-23 12:27:40 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Henry Cook
16d0f522b0
[tracegen] filter seed report
2016-11-23 12:09:09 -08:00
Henry Cook
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
Wesley W. Terpstra
cf8ecbd53b
travis: balance regression tasks a bit more fairly
2016-11-23 10:28:22 -08:00
Wesley W. Terpstra
e8e95d4bcf
regression: remove cde submodule update
2016-11-23 10:28:22 -08:00
Wesley W. Terpstra
a93d34742a
rocketchip: bump all submodules (and remove cde)
2016-11-23 10:28:22 -08:00
Wesley W. Terpstra
612f96b2af
Merge pull request #447 from ucb-bar/axi4-master
...
Axi4 master
2016-11-23 10:23:43 -08:00
Wesley W. Terpstra
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
1e7d597fd3
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
Wesley W. Terpstra
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
Wesley W. Terpstra
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
...
This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
Wesley W. Terpstra
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
Wesley W. Terpstra
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
Wesley W. Terpstra
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
