cf716fea58
fix mm_dramsim2
2016-03-29 20:16:07 -07:00
8c73d10fe1
Support SCR address generation with __OFFSET at the end
2016-02-25 21:57:37 -08:00
a073c37e36
The FPGA doesn't have an HTIF clock divider
...
We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code. This patch just doesn't write the HTIF SCR when
there isn't one.
2016-02-22 16:15:07 -08:00
926efd0cab
Allow the number of memory channels to be picked at runtime
...
We're building a chip with 8 memory channels. Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels. This commit adds a SCR that controls the number of active
memory channels on a chip. Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.
By default this just adds a 1-bit SCR, which essentially no extra logic.
When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration. The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.
A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
db9de94588
Generate and use SCR address header files
...
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
6fc1e92708
add option to print cycle count regardless of exit status
2015-12-04 12:04:13 -08:00
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
ba5a6af05c
correctly stripe data across memory channels in simulation
2015-11-05 10:48:32 -08:00
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
c517d9f6e3
fix htif emulator constructor in vcs_main
2015-09-25 17:21:09 -07:00
5e3f9115d3
make sure HTIF mem_mb doesn't exceed MMIOBase
2015-09-25 09:02:35 -07:00
f200d0947a
Force C++ emulator to always use 1GB for MEM_SIZE
...
Fixes #17
2015-09-24 23:56:41 -04:00
fbc6e695d3
remove bugs from float_fix
2015-09-23 16:11:47 -07:00
56daea793a
allow float_fix to take stdin (for piping)
2015-09-23 16:09:09 -07:00
38a9b23ce7
add a flag to only log and dump after a certain number of cycles
2015-09-22 10:32:31 -07:00
4496e8d4e2
make sure htif_emulator properly sets memory size
2015-09-22 10:32:31 -07:00
de81762f7c
faster and more conservative float_fix
2015-09-15 17:19:29 -07:00
7e25b1ce03
cleaner/faster comlog without linear search
2015-09-15 17:19:29 -07:00
3eed7ff238
make float_fix more conservative with replacement
2015-09-12 11:00:00 -07:00
a12cd13190
tool to unrecode single floats from commit logs
2015-09-11 20:19:18 -07:00
c8a7deb950
Added a commitlog post-processor for Rocket
...
- Useful for taking Rocket's out-of-order writebacks and generating an
in-order commit log.
- Resulting commit log can be diffed against Spike's commit log.
2015-09-11 16:06:01 -07:00
0ac6172525
Add "-memsize" flag to emulator
...
- Allow user to set memory size (in MiB) used by emulator.
- if memory is exhausted, warn user about memory shortage.
Close #3
2015-08-26 17:53:37 -07:00
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
...
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
275b72368b
add CONFIG to the name of simulator executable
2014-09-11 22:11:58 -07:00
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
d2c32b048a
fix bug in htif_fini, need to use vc_handle!
2014-03-18 01:35:08 -07:00
0d124d283a
Write our own vcs main() routine
2014-03-17 17:02:28 -07:00
7f23257873
Print out random seed if test fails
2014-03-17 15:35:32 -07:00
d055c0ebaf
Push rocket/hardfloat/chisel
2014-03-04 16:39:06 -08:00
dfc13236d1
Linux works again!
2014-01-16 12:44:29 -08:00
ab6cd9c9e8
Update chisel, rocket
2013-12-09 15:09:48 -08:00
c55eee7244
Pass target machine exit code back to host OS
2013-10-29 13:24:09 -07:00
fbdbb01232
update to new isa; disable vector tests
2013-09-12 17:04:03 -07:00
ae0716fb6d
Use chisel printf for logging
2013-06-13 10:53:23 -07:00
cfa86dba4f
add FPGA test bench
...
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
d2e1828714
gracefully kill htif thread, fixing tty stuff
2013-05-02 04:59:32 -07:00
def11e44b8
don't pipe stdout to vcd2vpd
2013-03-25 17:01:13 -07:00
c6695bee7c
fix emulator HTIF interface bug
2013-02-20 16:11:21 -08:00
dbb61306f0
randomize coreid mapping
2013-01-26 16:13:14 -08:00
4077b22929
include fesvr as a library; improve harnesses
2013-01-24 23:57:23 -08:00
f37b9d9a7d
fix dramsim2 memory model to wrap around
...
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
2013-01-23 01:40:15 -08:00
bbd010750f
add missing #include
2013-01-06 04:53:40 -08:00
d911e635d6
simplify c++ memory models; support +dramsim flag
...
works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
6d47d18c2b
catch sigterm to gracefully exit (fixes vcd)
2012-11-20 05:40:44 -08:00
b58214d7e3
remove more global constants
2012-11-17 17:25:43 -08:00
cf05b604b3
upgrade to new rocket; improve vlsi makefiles
2012-11-17 07:21:29 -08:00
