Wesley W. Terpstra
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40daea2e15
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util: Config scheme supporting up with ++
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2016-11-18 16:18:30 -08:00 |
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Wesley W. Terpstra
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e5febcfa33
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rocketchip: there are no more useful parameters to dump
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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30425d1665
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rocketchip: eliminate all Knobs
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2016-11-18 14:31:42 -08:00 |
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Wesley W. Terpstra
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119ccae9af
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rocketchip: don't use explicit cde namespace
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2016-11-18 14:31:42 -08:00 |
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Richard Xia
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87cbd5c893
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Merge pull request #439 from ucb-bar/add-chip-configs
Add various granular configs.
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2016-11-18 12:12:50 -08:00 |
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Richard Xia
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bab504cc3f
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Add various granular and composable configs.
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2016-11-18 11:30:07 -08:00 |
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Henry Cook
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5bd343bac8
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[rocket] d_last && d.fire() => d_done
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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1ddccb1b33
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[rocket] add TODO for single cycle ack
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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94086f2270
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[tl2] broadcast hub probe port width bugfix
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2016-11-17 18:42:59 -08:00 |
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Henry Cook
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960c2723ab
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[tl2] MemoryOpCategories: use def to supply Cat'd consts
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2016-11-17 18:42:59 -08:00 |
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Wesley W. Terpstra
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179c93db42
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tilelink2 broadcast: make it controlled via Config
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2016-11-17 17:26:49 -08:00 |
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Wesley W. Terpstra
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f4ca5ea1f3
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rocketchip: match simulated memory width to ExtMem.beatBytes
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2016-11-17 15:40:47 -08:00 |
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Wesley W. Terpstra
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12d0d8bea2
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rocketchip: remove obsolete bus configuration
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2016-11-17 14:30:15 -08:00 |
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Wesley W. Terpstra
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c82b371354
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rocketchip: remove obsolete TL1 config
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2016-11-17 14:24:45 -08:00 |
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Wesley W. Terpstra
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dfc3a0dafb
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tilelink2: do not depend on obsolete TL1 configuration
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2016-11-17 14:07:53 -08:00 |
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Wesley W. Terpstra
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8a0ecdaaad
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groundtest: ComparatorConfig lives again
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2016-11-17 11:07:49 -08:00 |
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Henry Cook
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92e233d596
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[groundtest] testramaddr constant in package
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2016-11-16 18:42:56 -08:00 |
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Henry Cook
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e1992d7c55
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[rocket] grant addr bugfix
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2016-11-16 18:12:06 -08:00 |
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Henry Cook
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84f249bd03
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[rocketchip] BigInt cast
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2016-11-16 18:11:06 -08:00 |
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Henry Cook
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da7ecfd189
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[rocket] probeack vs probeackdata bugfix
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2016-11-16 17:27:02 -08:00 |
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Henry Cook
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75d4347192
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[groundtest] runs tests with new coreplex and top
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2016-11-16 17:05:53 -08:00 |
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Henry Cook
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24e3216fcf
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coreplex: allow zero interrupt sink/sources
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2016-11-16 16:50:36 -08:00 |
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Henry Cook
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479bc82f03
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tilelink2 Broadcast: improve bufferless throughput
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2016-11-16 16:50:36 -08:00 |
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Henry Cook
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408e78e35e
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rocketchip Periphery: ExtMem and ExtBus Configs
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2016-11-16 16:50:30 -08:00 |
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Henry Cook
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1f51564577
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[rocket] dcache probe ack data bugfix
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2016-11-16 14:25:21 -08:00 |
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Henry Cook
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66a2c5544e
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[rocket] L1D acquire addr bugfix
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2016-11-16 13:38:52 -08:00 |
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Henry Cook
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c5e03c9c76
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[rocket] dcache release addr bugfix
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2016-11-16 13:14:51 -08:00 |
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Richard Xia
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81d98304dc
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Merge pull request #438 from ucb-bar/bump-riscv-tools-for-riscv-test-updates
Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization feature.
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2016-11-16 12:26:48 -08:00 |
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Wesley W. Terpstra
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06a7b95d0d
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tilelink2 broadcast: support bufferless Config
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2016-11-16 12:25:11 -08:00 |
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Wesley W. Terpstra
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3703ed39f7
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groundtest: PTW needs atomics
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2016-11-16 12:16:54 -08:00 |
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Wesley W. Terpstra
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5d2e637a4a
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tilelink2 Legacy: uncached TL never needs manager_xact_id
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2016-11-16 12:16:25 -08:00 |
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Richard Xia
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6e5dd45f9a
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Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization fix.
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2016-11-16 11:33:15 -08:00 |
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Wesley W. Terpstra
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10e459fedb
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rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
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2016-11-15 18:27:52 -08:00 |
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Henry Cook
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2d68f12115
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[tl2] give groundtest tile some output nodes
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2016-11-14 18:09:40 -08:00 |
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Wesley W. Terpstra
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ab3dafb8bc
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Monitor: restore Probe&Acquire checks
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2016-11-14 15:36:52 -08:00 |
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Wesley W. Terpstra
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385b5d5698
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axi4: default should be GET_EFFECTS
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2016-11-14 15:19:39 -08:00 |
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Henry Cook
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0e30364f56
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WIP
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2016-11-14 13:39:01 -08:00 |
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Henry Cook
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c0efd247b0
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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Henry Cook
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b7730d66f2
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WIP bugfixes: run until corrupted WB data (beats repeated)
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2016-11-11 18:34:48 -08:00 |
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Henry Cook
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71315d5cf5
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WIP scala compile and firrtl elaborate; monitor error
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2016-11-11 13:07:45 -08:00 |
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Henry Cook
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afa1a6d549
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WIP uncore and rocket changes compile
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2016-11-10 15:57:29 -08:00 |
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Wesley W. Terpstra
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32fd11935c
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rocketchip: use TL2 and AXI4 for memory subsytem
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2016-11-04 13:36:47 -07:00 |
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Wesley W. Terpstra
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9d77e34bee
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tilelink2 Filter: make transfer cap robust against large filters
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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4a2cf6431b
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coreplex: make 'mem' port an Option until we can use a Seq
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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8f757a9135
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coreplex: rename BankedL2 trait to BankedL2CoherenceManagers
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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b8df59f43b
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tilelink2 Broadcast: support "bufferless" implementation
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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14800f8fb4
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tilelink2 Broadcast: only support caching readable devices
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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d03046d11c
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coreplex: fix BankedL2 line width
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2016-11-04 13:35:36 -07:00 |
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Wesley W. Terpstra
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ea602790a8
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Merge pull request #432 from ucb-bar/tl2-address-filtering
Tl2 address filtering
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2016-11-04 00:12:43 -07:00 |
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Wesley W. Terpstra
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da3cc3b299
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coreplex: TileLink2 l1tol2 memory channels
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2016-11-03 22:18:28 -07:00 |
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