riscv/rocket-chip
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Author SHA1 Message Date
Schuyler Eldridge
c61714a465 Pass MODEL variable to emulator.cc 
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
 2017-03-30 02:08:01 -07:00
Andrew Waterman
fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
Alex Solomatnikov
9f85b2e996 Do allow make to remove .vpd files on Ctrl-C 2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Andrew Waterman
8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Wesley W. Terpstra
ed38787c36 Merge pull request #622 from ucb-bar/priv-1.10 
Various priv-1.10 changes
 2017-03-27 19:28:30 -07:00
Andrew Waterman
05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Megan Wachs
ab300f7985 Update README_TRAVIS.md 2017-03-27 17:45:50 -07:00
Megan Wachs
3fc74f3d08 Create README_TRAVIS.md 2017-03-27 17:45:46 -07:00
Andrew Waterman
d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
a2a3346e73
 2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Megan Wachs
861651587b debug: Update Makefile to use new OpenOCD and allow for easier debugging. (#619) 2017-03-27 15:52:04 -07:00
Megan Wachs
7014263c29 Update LICENSE.SiFive (#618) 
Bump the year for the SiFive license
 2017-03-27 14:55:28 -07:00
Megan Wachs
70fa10fc55 Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615) 2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Wesley W. Terpstra
722b0d521f bootrom: also setup SBI a0+a1 for when we hang (#617) 
This way a program started by the debugger still has the DTB handy.
 2017-03-27 00:01:05 -07:00
Megan Wachs
11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice. 
This allows more flexibility e.g. considering the ROM as part of other
devices.
 2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. 2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be Add ucb-art/chisel-jtag (#612) 
* jtag: Add ucb-art/chisel-jtag to junctions.

* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch

* jtag: move to a top-level package
 2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10 Implement new FP encoding proposal 
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067 Fix groundtest to provide missing signals to TLB 2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
986e1754be Merge pull request #611 from ucb-bar/expose-back-side-bus 
rename l2FrontendBus as fsb, expose bsb
 2017-03-24 23:32:50 -07:00
Wesley W. Terpstra
537274b645 coreplex: move buffers inside the coreplex 
This should make hierarchical place and route easier.
 2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078 rename l2FrontendBus as fsb, expose bsb 2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
19485a9861 Merge pull request #609 from ucb-bar/dtb-rom 
DTB in the bootrom
 2017-03-24 21:54:13 -07:00
Wesley W. Terpstra
e74226564c travis: add dependency on device-tree-compiler 2017-03-24 20:59:33 -07:00
Wesley W. Terpstra
f36b1766f8 TLROM: use the smallest ROM implementation that works 
The contents everywhere else are still zero.
 2017-03-24 20:40:28 -07:00
Wesley W. Terpstra
ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00