riscv/rocket-chip
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2271 Commits

Author SHA1 Message Date
Wesley W. Terpstra
60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope 2017-10-26 15:19:05 -07:00
Wesley W. Terpstra
a060c37173 diplomacy: expose the API to query a Node for its neighbours 2017-10-26 15:08:06 -07:00
Wesley W. Terpstra
e2d6d4d725 diplomacy: eliminate bindings dead-code 2017-10-26 15:02:21 -07:00
Wesley W. Terpstra
9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
2acff8d21f util: delete old long-deprecated crossing code 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
da7703aee9 crossings: deprecate non-island crossing style 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
76df1397e0 crossings: stop using deprecated APIs in tests 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
380cc6f03b axi4: now also supports the island pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
ce2b904b19 coreplex: tidy up interrupt crossings 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e30906589f coreplex: refactor crossings to use node pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
6276ea4291 diplomacy: it possible for NodeHandles to put indirection on their attachment 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
8c5e8dd071 coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e894d64bca diplomacy: support := composition 
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...

It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
 2017-10-26 13:04:32 -07:00
Henry Cook
b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry Cook
9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry Cook
95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
2175758050 interrupts: implement in crossing wrapper 2017-10-26 13:04:29 -07:00
Wesley W. Terpstra
c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Wesley W. Terpstra
6bc9c9fc6c coreplex: add a crossing wrapper to generalize the island pattern 2017-10-25 16:56:50 -07:00
Wesley W. Terpstra
7453186b59 diplomacy: add reflection for parent modules to nodes 2017-10-25 16:56:50 -07:00
Christopher Celio
c4978712c9 csr: allow for superscalar decode (#1069) 
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
 2017-10-25 13:58:26 -07:00
Wesley W. Terpstra
82b1aa8116 coreplex: print the A first to look nicer 2017-10-18 16:52:35 -07:00
Wesley W. Terpstra
a1ac23d7ec coreplex: continue to print the device name in the address map 2017-10-18 16:44:53 -07:00
Richard Xia
5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Megan Wachs
e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) 
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
 2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259 Expand C.UNIMP correctly (#1052) 
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
 2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426 axi4: implement a diplomatic AXI4 clock crossing (#1049) 2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Megan Wachs
7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Henry Cook
60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook
2dbe882e58 tilelink: add BasicBusBlocker device 2017-10-11 13:36:42 -07:00
Henry Cook
9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice 2017-10-11 12:45:36 -07:00
Henry Cook
ec056535dc tilelink: add DeadlockDevice 2017-10-11 12:44:23 -07:00
Wesley W. Terpstra
b566ffedea system: fix DefaultFPGAConfig (#1047) 
It was missing cores. Fixes #736.
 2017-10-11 10:48:41 -07:00
Henry Cook
329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook
1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Wesley W. Terpstra
5d62c321f4 generator: create annotation file 2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
b3bdf5eca6 RegField: default argument for .bytes 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5 clint: use RegField.toBytes to save some work 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296 diplomacy: auto connect bundles in a stable order (#1045) 2017-10-10 19:41:46 -07:00
Henry Cook
1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) 2017-10-10 17:14:33 -07:00
Henry Cook
37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook
8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook
660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Andrew Waterman
50429daef4 Merge pull request #1036 from freechipsproject/l1-cover 
Add some covers for L1 memory system
 2017-10-10 12:28:48 -07:00
Henry Cook
9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Wesley W. Terpstra
d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman
1474ab438d Remove extraneous signal 2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Andrew Waterman
2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Megan Wachs
0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs
0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs
9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Andrew Waterman
986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60 Don't route branch comparison result through ALU output mux 
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
 2017-10-07 17:36:24 -07:00
Andrew Waterman
36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles
5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles
7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Wesley W. Terpstra
bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030) 
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
 2017-10-05 12:49:49 -07:00
Wei Song (宋威)
81b9ac42a3 add comments to diplomacy resource. (#913) 2017-10-05 12:45:56 -07:00
Henry Cook
8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Andrew Waterman
5a84564203 Merge pull request #1023 from freechipsproject/csr-cleanup 
Generalize CSR file to support simpler cores
 2017-10-04 14:04:59 -07:00
Andrew Waterman
32fda51a2c Get rid of paddrBits from SystemBus (#1029) 2017-10-04 12:11:37 -07:00
Andrew Waterman
7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend 
It is more generally useful.
 2017-10-03 17:34:18 -07:00
Andrew Waterman
2786e42d99 Don't register interrupts in CSRFile 
They are usually registered outside the tile in a CDC.
 2017-10-03 17:34:18 -07:00
Andrew Waterman
5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Andrew Waterman
190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Henry Cook
5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid 
Make use of the new DontTouch annotation
 2017-10-03 12:55:34 -07:00
Henry Cook
d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook
aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Henry Cook
cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire 
which contains hartid.
 2017-10-02 19:36:10 -07:00
Wesley W. Terpstra
a2dc13669a Error grants (#1025) 
* CacheCork: an error Grant still says 'toT' even though it is transient

Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.

This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.

* Error: handle permissions properly
 2017-10-02 14:49:25 -07:00
Megan Wachs
9c9cb68462 JTAG Coverage: Add reset coverage points 2017-10-02 11:08:13 -07:00
Megan Wachs
a8ab06d572 JTAG: Add coverage points to the JTAG Tap 2017-10-02 11:08:13 -07:00
Jack Koenig
8891bf1b64 Bump chisel3 and firrtl, update plugin versions 
And update chisel3 code
 2017-09-29 15:44:27 -07:00
Henry Cook
547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Andrew Waterman
9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn 
Provide correct trace insn on interrupts when possible
 2017-09-27 18:47:24 -07:00
Andrew Waterman
9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Wesley W. Terpstra
0a287df0f7 Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles 2017-09-27 16:28:10 -07:00
Andrew Waterman
31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Wesley W. Terpstra
feae216f05 clint: output interrupts in the correct direction 2017-09-27 15:18:42 -07:00
Henry Cook
05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook
652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Wesley W. Terpstra
9307092d14 coreplex: draw the FrontBus at the bottom and SystemBus at the top 2017-09-27 14:20:39 -07:00
Henry Cook
f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Andrew Waterman
78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Wesley W. Terpstra
e07d86aecd rocket: flip interrupt rendering so cores are on top 2017-09-27 12:46:29 -07:00
Andrew Waterman
583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra
1fda05970a rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:33:08 -07:00
Wesley W. Terpstra
ce01ab2700 RegisterRouter: correctly create interrupts vector 2017-09-27 12:27:16 -07:00
Wesley W. Terpstra
0268959c24 rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:02:04 -07:00
Wesley W. Terpstra
e35d3df6ea diplomacy: detect and report cycles in the diplomatic graph 2017-09-27 11:46:06 -07:00
Wesley W. Terpstra
5af08966d8 coreplex: fix WithoutTLMonitors 
closes #1017
 2017-09-27 00:57:18 -07:00
Wesley W. Terpstra
d87536ff8b diplomacy: make NodeHandle recursively composable 2017-09-26 18:47:16 -07:00
Wesley W. Terpstra
31a934bec0 coreplex: buses are now LazyModules with LazyScope 2017-09-26 14:58:56 -07:00
Wesley W. Terpstra
da40573a64 diplomacy: replace LazyModule.stack with an optional scope 2017-09-26 14:56:50 -07:00
Wesley W. Terpstra
a2b423d647 diplomacy: add LazyScope to post-hoc add children to a LazyModule 2017-09-26 14:40:45 -07:00
Wesley W. Terpstra
a27e853101 diplomacy: move rendering properties to edges 
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
 2017-09-26 13:24:36 -07:00
Wesley W. Terpstra
76c2aa1661 diplomacy: introduce the typing-saving SimpleNodeImp 2017-09-26 12:28:59 -07:00
Wesley W. Terpstra
870ed3d219 diplomacy: fix the order of auto signals 2017-09-26 11:56:55 -07:00
Wesley W. Terpstra
d22ec1eddf diplomacy: beautify node signal prefixes 2017-09-26 11:56:53 -07:00
Henry Cook
9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
Wesley W. Terpstra
fef5054cec diplomacy: disambiguate names only when necessary 
If two (or more) 'auto_' things have the same name, append _0 and _1 to them.

The order of definitions is unaffected; ie:
  a => a_0
  b => b_0
  b => b_1
  c => c
  a => a_1
 2017-09-25 16:12:34 -07:00
Wesley W. Terpstra
5323cf88dd util: add Option.unzip 2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
bc225a4e82 diplomacy: place Monitors inside LazyModules sinks 
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.

Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
 2017-09-22 23:36:17 -07:00
Wesley W. Terpstra
cfb7f13408 diplomacy: capture SourceInfo at point of := in Edge parameters 2017-09-22 22:25:56 -07:00
Wesley W. Terpstra
16969eb1f6 diplomacy: spelling fix 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
53f6999ea8 Splitter: reuse TLCustom node instead of special diplomacy case 2017-09-22 14:58:39 -07:00
Wesley W. Terpstra
6fa5250e1f config: fix warning 2017-09-22 14:58:36 -07:00
Wesley W. Terpstra
17ba209ed0 coreplex: name LazyModules 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
1fedabcb55 tilelink: invoke LazyModule() at point of monitor binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
dfc815f4d3 rocket: invoke LazyModule at point of use/binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
87d597c70d ahb apb: remove unintentional var 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
3656e975a1 diplomacy: ValName captures val bindings for Nodes 2017-09-22 14:38:47 -07:00
Henry Cook
81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook
e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman
88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman
6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman
9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman
026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman
5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman
f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman
db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman
aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
dbf599f6a1 Support SynchronizerShiftReg(sync = 0) 
This makes it easier to parameterize code where the synchronizer
might not always be needed.
 2017-09-20 00:05:07 -07:00
Andrew Waterman
79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman
ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
9a175b0fb1 Statically report error correction/detection capability from ECC codes 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Andrew Waterman
acea94bcef Merge pull request #1001 from freechipsproject/address-decoder 
Address decoder "improvements"
 2017-09-19 22:38:53 -07:00
Jacob Chang
b4fc5104d4 Add cover property API that can be refined through Config PropertyLibrary (#998) 2017-09-19 19:26:54 -07:00
Henry Cook
57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Andrew Waterman
87b92cb206 Scan AddressDecoder bits left to right 
This heuristic is brittle but fixes deduplication in RocketTile.
 2017-09-19 17:47:24 -07:00
Andrew Waterman
72bd89a2af Add another AddressDecoder debug message 2017-09-19 17:47:17 -07:00
Andrew Waterman
fb2ad11347 Improve AddressDecoder optimization function 
This function is better 27% of the time but worse 6% of the time.
 2017-09-19 17:47:12 -07:00
Henry Cook
8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Megan Wachs
826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset 2017-09-18 09:50:27 -07:00
Andrew Waterman
d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Megan Wachs
c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
Megan Wachs
215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
Henry Cook
9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Megan Wachs
641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
Megan Wachs
6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
Megan Wachs
ffc514d1bc test_mode_reset: Add missing file 2017-09-14 13:17:37 -07:00
Megan Wachs
a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
Megan Wachs
44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
Megan Wachs
82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
Henry Cook
e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook
56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook
b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook
37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry Cook
063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Andrew Waterman
1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Henry Cook
9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook
3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook
e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts 
Add Parameters to diplomatic edges
 2017-09-08 13:16:11 -07:00
Andrew Waterman
53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Wesley W. Terpstra
e723a3f42b MemoryBus: fanout the A for performance 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6879f5bfb1 tilelink: Xbar now allows for fanout control 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
e831acba9c adapters: support bulk connections 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
06a244f9f9 diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
bef593c21a diplomacy: edges now capture their Parameters 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80ed27683e diplomacy: protect against API leakage 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744 tilelink: Monitor construction method is unconditional 
Whether or not a Monitor should be placed is decided by diplomacy.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
7a8364ef08 diplomacy: leverage new Parameters defaults 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
655a08f12e config: support default values for Field[T] keys 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
09d8d476c5 config: require Parameters keys to be Field[T] 
This has been good practice for ages. Enforce it.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
42f1ae27fc Xbar: use the IdentityModule to encourage wider fanout 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
5626cdd18f util: add the IdentityModule, useful to dedup wires 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193 coreplex: add externalSlaveBuffers configuration option 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910 coreplex: rename externalBuffers to externalMasterBuffers 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f tilelink Bus: toAsyncSlaves now supports BufferChains 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49 tilelink: add Bus.toSyncSlaves for easy BufferChain attachment 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59 tilelink: Bus.toRationalSlaves can have a BufferChain 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230 tilelink Buffer: use new :=? adapter API 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6 diplomacy: support :=? for unknown star inference 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf config: support p.lift(key) to optionally return a value 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71 RationalCrossing: use ShiftQueues 
These are faster and small don't cost much more.
 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd ShiftQueue: added a helper object 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256 ShiftQueue: fix bug in !flow case 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd plic: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6 clint: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254 synchronizers: I learn how foldRight works 2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. 2017-09-07 09:57:50 -07:00
Megan Wachs
dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-06 11:07:19 -07:00
Megan Wachs
3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary 2017-09-06 10:37:59 -07:00
Jim Lawson
f1b7666d21 Jtagresettobool - add explicit toBool cast now required on reset. (#984) 
Add explicit toBool cast on reset, for chisel3 compatability
 2017-09-06 09:49:47 -07:00
Megan Wachs
777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00
Wesley W. Terpstra
b1cacc56ad SystemBus: restore correct order of FIFOFixer and Buffer 2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb FrontBus: FIFOFixer should not have a buffer between it and Xbar 2017-09-05 16:27:57 -07:00
Megan Wachs
e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. 2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514 Synchronizers: remove some newlines and unncessary gen's 2017-09-05 15:17:21 -07:00
Wesley W. Terpstra
e65f49b89a FrontBus: attach to splitter for cross-chip visibility 2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a sbus => pbus: 2 buffers should already be enough 
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.
 2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming 2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c pbus: turn down overkill buffering between PBus and SBus 2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0 buses: name dummy buffers too 2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35 frontbus: Name the connection. 2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66 buses: Name all the things. 2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Megan Wachs
183fefb2b9 Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in 2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda SystemBus: add stupidly many (4 more) buffers from sbus=>pbus 
This should probably be reverted.
 2017-08-30 14:22:49 -07:00
Henry Styles
f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter 2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
173f185b17 Merge pull request #976 from freechipsproject/system-buffer 
SystemBus: add output buffering
 2017-08-30 23:22:13 +02:00
Wesley W. Terpstra
656609d610 SystemBus: split FIFOFixers along bus boundaries 
If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
 2017-08-30 13:28:11 -07:00
Megan Wachs
a3bc5f2e33 synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive 2017-08-30 12:59:16 -07:00
Megan Wachs
8139014c9e syncrhonizers: Remove unused sync from superclass 2017-08-30 12:33:03 -07:00
Megan Wachs
9dd6c4c32d synchronizers: New chisel ways of cloning type and use simpler lambda function 2017-08-30 12:11:14 -07:00
Megan Wachs
bd32f0c122 synchronizers: properly pass parameters up to the superclass 2017-08-30 11:58:25 -07:00
Megan Wachs
483e63da19 synchronizers: Correctly pass the width through 2017-08-30 11:50:25 -07:00
Megan Wachs
a62ce0afe6 TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer. 2017-08-29 10:36:46 -07:00
Megan Wachs
c473538e36 Merge remote-tracking branch 'origin/master' into async_reg 2017-08-28 17:19:03 -07:00
Megan Wachs
451334ac73 Add 1-deep synchronizer register for output of AsyncQueue 2017-08-28 17:18:54 -07:00
Wesley W. Terpstra
bf19440db5 SystemBus: use a full buffer on slaves 2017-08-26 02:47:04 -07:00
Megan Wachs
85c39b2f97 syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI 2017-08-24 17:47:04 -07:00
Megan Wachs
4e773f4738 syncregs: Use synchronizer primivites for LevelSyncCrossing 2017-08-24 17:42:31 -07:00
Megan Wachs
130b24355f syncregs: Use synchronizer primitives for IntXing 2017-08-24 17:39:07 -07:00
Megan Wachs
8b462d1595 syncregs: Use common primitives for AsyncQueue grey code synchronizers 2017-08-24 17:34:07 -07:00