axi4: implement a diplomatic AXI4 clock crossing (#1049)
This commit is contained in:
Wesley W. Terpstra
GitHub
parent
b64609bfe8
commit
f82e441426
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@ -0,0 +1,119 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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class AXI4AsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AsyncSourceNode(sync)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val depth = edgeOut.slave.depth
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out.ar <> ToAsyncBundle(in.ar, depth, sync)
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out.aw <> ToAsyncBundle(in.aw, depth, sync)
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out. w <> ToAsyncBundle(in. w, depth, sync)
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in .r <> FromAsyncBundle(out.r, sync)
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in .b <> FromAsyncBundle(out.b, sync)
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}
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}
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}
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class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AsyncSinkNode(depth, sync)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out.ar <> FromAsyncBundle(in.ar, sync)
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out.aw <> FromAsyncBundle(in.aw, sync)
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out. w <> FromAsyncBundle(in. w, sync)
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in .r <> ToAsyncBundle(out.r, depth, sync)
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in .b <> ToAsyncBundle(out.b, depth, sync)
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}
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}
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}
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object AXI4AsyncCrossingSource
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{
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// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSource()(x.node)
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def apply(sync: Int = 3)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4AsyncOutwardNode = {
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val source = LazyModule(new AXI4AsyncCrossingSource(sync))
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source.node :=? x
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source.node
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}
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}
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object AXI4AsyncCrossingSink
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{
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// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSink()(x.node)
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def apply(depth: Int = 8, sync: Int = 3)(x: AXI4AsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
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sink.node :=? x
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sink.node
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}
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}
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class AXI4AsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val source = LazyModule(new AXI4AsyncCrossingSource(sync))
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val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
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val node = NodeHandle(source.node, sink.node)
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sink.node := source.node
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val in_clock = Clock(INPUT)
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val in_reset = Bool(INPUT)
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val out_clock = Clock(INPUT)
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val out_reset = Bool(INPUT)
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})
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source.module.clock := io.in_clock
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source.module.reset := io.in_reset
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sink.module.clock := io.out_clock
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sink.module.reset := io.out_reset
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}
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}
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
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val model = LazyModule(new TLRAMModel("AsyncCrossing"))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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val fuzz = LazyModule(new TLFuzzer(txns))
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val toaxi = LazyModule(new TLToAXI4(beatBytes = 4))
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val cross = LazyModule(new AXI4AsyncCrossing)
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model.node := fuzz.node
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toaxi.node := model.node
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cross.node := toaxi.node
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ram.node := cross.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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// Shove the RAM into another clock domain
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val clocks = Module(new Pow2ClockDivider(2))
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ram.module.clock := clocks.io.clock_out
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// ... and safely cross AXI42 into it
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cross.module.io.in_clock := clock
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cross.module.io.in_reset := reset
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cross.module.io.out_clock := clocks.io.clock_out
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cross.module.io.out_reset := reset
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}
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}
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class AXI4RAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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io.finished := Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module).io.finished
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}
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@ -4,7 +4,7 @@ package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.Irrevocable
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import freechips.rocketchip.util.GenericParameterizedBundle
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import freechips.rocketchip.util._
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abstract class AXI4BundleBase(params: AXI4BundleParameters) extends GenericParameterizedBundle(params)
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@ -76,3 +76,14 @@ object AXI4Bundle
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{
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def apply(params: AXI4BundleParameters) = new AXI4Bundle(params)
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}
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class AXI4AsyncBundleBase(params: AXI4AsyncBundleParameters) extends GenericParameterizedBundle(params)
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class AXI4AsyncBundle(params: AXI4AsyncBundleParameters) extends AXI4AsyncBundleBase(params)
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{
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val aw = new AsyncBundle(params.depth, new AXI4BundleAW(params.base))
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val w = new AsyncBundle(params.depth, new AXI4BundleW (params.base))
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val b = new AsyncBundle(params.depth, new AXI4BundleB (params.base)).flip
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val ar = new AsyncBundle(params.depth, new AXI4BundleAR(params.base))
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val r = new AsyncBundle(params.depth, new AXI4BundleR (params.base)).flip
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}
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@ -28,3 +28,25 @@ case class AXI4AdapterNode(
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implicit valName: ValName)
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extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
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case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp)()
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object AXI4AsyncImp extends SimpleNodeImp[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncEdgeParameters, AXI4AsyncBundle]
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{
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def edge(pd: AXI4AsyncMasterPortParameters, pu: AXI4AsyncSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4AsyncEdgeParameters(pd, pu, p, sourceInfo)
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def bundle(e: AXI4AsyncEdgeParameters) = new AXI4AsyncBundle(e.bundle)
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def render(e: AXI4AsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.slave.depth.toString)
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override def mixO(pd: AXI4AsyncMasterPortParameters, node: OutwardNode[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]): AXI4AsyncMasterPortParameters =
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pd.copy(base = pd.base.copy(masters = pd.base.masters.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: AXI4AsyncSlavePortParameters, node: InwardNode[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]): AXI4AsyncSlavePortParameters =
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pu.copy(base = pu.base.copy(slaves = pu.base.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class AXI4AsyncSourceNode(sync: Int)(implicit valName: ValName)
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extends MixedAdapterNode(AXI4Imp, AXI4AsyncImp)(
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dFn = { p => AXI4AsyncMasterPortParameters(p) },
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uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain
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case class AXI4AsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
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extends MixedAdapterNode(AXI4AsyncImp, AXI4Imp)(
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dFn = { p => p.base },
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uFn = { p => AXI4AsyncSlavePortParameters(depth, p) })
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@ -131,3 +131,12 @@ case class AXI4EdgeParameters(
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{
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val bundle = AXI4BundleParameters(master, slave)
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}
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case class AXI4AsyncSlavePortParameters(depth: Int, base: AXI4SlavePortParameters) { require(isPow2(depth)) }
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case class AXI4AsyncMasterPortParameters(base: AXI4MasterPortParameters)
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case class AXI4AsyncBundleParameters(depth: Int, base: AXI4BundleParameters) { require (isPow2(depth)) }
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case class AXI4AsyncEdgeParameters(master: AXI4AsyncMasterPortParameters, slave: AXI4AsyncSlavePortParameters, params: Parameters, sourceInfo: SourceInfo)
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{
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val bundle = AXI4AsyncBundleParameters(slave.depth, AXI4BundleParameters(master.base, slave.base))
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}
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@ -8,4 +8,5 @@ import freechips.rocketchip.diplomacy.OutwardNodeHandle
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package object axi4
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{
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type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4AsyncOutwardNode = OutwardNodeHandle[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]
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}
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@ -30,7 +30,8 @@ class WithAMBAUnitTests extends Config((site, here, up) => {
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Module(new APBBridgeTest(false,txns=6*txns, timeout=timeout)),
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Module(new AXI4LiteFuzzRAMTest(txns=6*txns, timeout=timeout)),
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Module(new AXI4FullFuzzRAMTest(txns=3*txns, timeout=timeout)),
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Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout))) }
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Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout)),
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Module(new AXI4RAMAsyncCrossingTest(txns=3*txns, timeout=timeout))) }
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})
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class WithTLSimpleUnitTests extends Config((site, here, up) => {
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