Megan Wachs e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) ... * Add a check that MaxHartIdBits is enough for all hartids * Correct off-by-one error in hartid check		2017-10-13 15:20:35 -07:00
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amba	axi4: conversion from TL does not need beatBytes (#1051)	2017-10-12 16:41:54 -07:00
config	config: fix warning	2017-09-22 14:58:36 -07:00
coreplex	axi4: conversion from TL does not need beatBytes (#1051)	2017-10-12 16:41:54 -07:00
devices	Merge pull request #1039 from freechipsproject/tile-crossing-params	2017-10-11 17:12:03 -07:00
diplomacy	diplomacy: auto connect bundles in a stable order (#1045)	2017-10-10 19:41:46 -07:00
groundtest	rocket: TIMs should never be cached	2017-10-11 18:22:52 -07:00
jtag	JTAG Coverage: Correct jtag_reset case	2017-10-09 09:54:15 -07:00
regmapper	RegField: default argument for .bytes	2017-10-10 19:49:35 -07:00
rocket	Expand C.UNIMP correctly (#1052)	2017-10-12 14:00:14 -07:00
system	Merge pull request #1039 from freechipsproject/tile-crossing-params	2017-10-11 17:12:03 -07:00
tile	Add a check that MaxHartIdBits is enough for all hartids (#1054)	2017-10-13 15:20:35 -07:00
tilelink	Merge pull request #1053 from freechipsproject/resource-cacheable	2017-10-12 17:49:49 -07:00
unittest	axi4: implement a diplomatic AXI4 clock crossing (#1049)	2017-10-12 00:05:45 -07:00
util	generator: create annotation file	2017-10-10 23:23:06 -07:00