c2b8b08461
tilelink: fix Fragmenter source re-use bug ( #888 )
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Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.
However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.
To solve this, we alternate an a.source bit every time D completes a txn.
2017-07-25 16:23:55 -07:00
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
f2002839eb
TLFragmenter: Continuing my spot battles on requires without explanatory strings ( #882 )
2017-07-21 21:55:32 -07:00
cf75c2049d
Merge pull request #878 from freechipsproject/fix-fifofixer
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tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 20:22:16 -07:00
21954c1c73
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 19:38:27 -07:00
4d784ad693
add cloneType to RegisterWriteIO and RegisterReadIO ( #874 )
2017-07-18 18:52:31 -07:00
8d793daf9c
Merge pull request #876 from freechipsproject/sq-helper
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ShiftQueue: support constant propagation
2017-07-18 16:30:23 -07:00
a9c58e9d9f
diplomacy: support creating ShiftQueues as well
2017-07-18 14:57:02 -07:00
c0a3bb58e9
ShiftQueue: use Vec of Bool to support constant prop of enq.valid
2017-07-18 14:56:59 -07:00
6d0821f19a
Update readme to reflect config name changes ( #871 )
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also update list of files expected to be seen in generated-src
2017-07-18 07:27:03 -07:00
416629b3bf
tilelink: FIFOFixer should fix no domain => domain cases ( #873 )
2017-07-17 22:32:17 -07:00
d09a985729
zero: fix attachment in multichannel case ( #870 )
2017-07-17 21:48:31 -07:00
fc75ada577
tilelink: Monitor should report line numbers of connection that failed ( #872 )
2017-07-17 21:29:14 -07:00
ec57994784
fix the TLFuzzer IO ( #869 )
2017-07-17 14:59:35 -07:00
16e8709144
tilelink: it is now legal to have errors on {Release,Hint}Ack ( #864 )
2017-07-14 16:13:30 -07:00
9ade7af013
Merge pull request #862 from freechipsproject/plic-max-pri-dts
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PLIC: Add maxPri as well as ndev in DTS
2017-07-13 17:08:21 -07:00
f0481801df
Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts
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Rename offchip-interrupts to external-interrupts.
2017-07-13 16:52:57 -07:00
35464782b5
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
d62787357b
Rename offchip-interrupts to external-interrupts.
2017-07-13 15:56:22 -07:00
f2533ce825
bootrom: Adding bootrom parameters ( #857 )
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BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
2017-07-13 13:40:02 -07:00
f646bed3ea
PLIC: Use longer DTS name for Max Priorities.
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I used the singular because there is really only one max priority
2017-07-13 13:37:22 -07:00
0800fd3ed9
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 13:18:50 -07:00
b7f1ba3428
tilelink: FIFOFixer must support null cases ( #860 )
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In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
2017-07-12 22:20:31 -07:00
0053a060ae
Merge pull request #859 from freechipsproject/fifo-fixer-configable
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Fifo fixer configable
2017-07-12 19:44:23 -07:00
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
09b9d33a9a
tilelink: FIFOFixer now has a policy parameter
2017-07-12 17:38:55 -07:00
b363a94480
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
c8a7648169
diplomacy: only evaluate a Nexus node's map function once
2017-07-12 16:20:55 -07:00
af3976aa67
regmapper: add byte-sized RegField helper function ( #854 )
2017-07-10 21:08:02 -07:00
177ccbb663
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was ( #855 )
2017-07-10 21:07:50 -07:00
287219da06
Merge pull request #851 from freechipsproject/chisel3clock
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Use chisel3 Clock() method.
2017-07-10 08:33:46 -07:00
29f5f77817
Merge pull request #853 from freechipsproject/sram-errors
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SRAM errors
2017-07-07 22:44:28 -07:00
5db0e770d5
tilelink: TestSRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
702143eb33
tilelink: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
9310a33e77
apb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
28fbf1af8e
ahb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
df44b23956
axi4: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
b2cc4b99ed
tilelink: TestSRAM reports errors on illegal access
2017-07-07 21:40:36 -07:00
e8cb6dafd3
tilelink: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
f1fb3be603
ahb: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
19851a7c9e
apb: SRAM reports errors on illegal access
2017-07-07 21:15:33 -07:00
025f7d890b
axi4: SRAM now reports errors on illegal address ( #852 )
2017-07-07 19:27:32 -07:00
2bf91a0558
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
c28c23150d
Merge pull request #850 from freechipsproject/plic_undefZero
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PLIC: (undefZero=true) Don't allow addresses to alias
2017-07-06 18:39:10 -07:00
76a1ae667f
PLIC: (undefZero=true) Don't allow addresses to alias
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While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
2017-07-06 17:57:08 -07:00
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
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L1 memory system improvements
2017-07-06 13:03:06 -07:00
