Christopher Celio
b55765f597
Bump riscv-tools
2015-08-26 16:08:45 -07:00
Christopher Celio
b1e845f370
Add space to README.md
2015-08-26 14:34:22 -07:00
Scott Beamer
b88c283b21
add travis support and tests
2015-08-25 13:29:20 -07:00
Scott Beamer
333c594d2a
respect environment's CXX
2015-08-25 13:26:14 -07:00
Scott Beamer
49ff021518
bump fpga repo
2015-08-21 15:39:59 -07:00
Henry Cook
bcf95b39e0
bump uncore
2015-08-10 20:08:50 -07:00
Henry Cook
a3c9431ee2
bump all submodules for scala version
2015-08-05 16:50:38 -07:00
Andrew Waterman
9b038db34a
Upgrade scala to 2.11.6
2015-08-05 15:37:03 -07:00
Andrew Waterman
700910adff
Chisel3 compatibility fix for <>
2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5
Various Chisel3 compatibility changes
2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6
Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
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Bump all submodules.
2015-07-29 18:15:45 -07:00
Henry Cook
ee531dc97e
Add missing changes to emulator/Makefile
2015-07-29 18:15:21 -07:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d
add zscale programs
2015-07-27 19:06:06 -07:00
Yunsup Lee
e571ebaf7f
bump zscale
2015-07-27 17:23:38 -07:00
Henry Cook
866396545d
For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten
2015-07-23 17:00:22 -07:00
Yunsup Lee
caf89baeb7
update zscale
2015-07-23 13:59:45 -07:00
Henry Cook
bd4ff35a4b
Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
2015-07-22 11:49:10 -07:00
Andrew Waterman
25e1412a33
Merge pull request #11 from ucb-bar/regression-fixes
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Regression script fixes
2015-07-20 12:58:54 -07:00
Palmer Dabbelt
d6b29ca9cc
Run regression with bash's "-ex" mode
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This causes every command to be echo'd to stderr, and any failing
command will fail the whole script. Without this the regression
script will always pass.
2015-07-20 12:21:19 -07:00
Palmer Dabbelt
9bbecffbb8
Have regression run "make" before "make run-asm-tests"
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I'm seeing some odd behavior where "make run-asm-tests" actually does
nothing. This works around the issue.
2015-07-20 12:20:32 -07:00
Yunsup Lee
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
Yunsup Lee
777facf91e
update tools
2015-07-17 12:33:19 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Henry Cook
1e977d12f2
Update README.md
2015-07-15 16:25:04 -07:00
Yunsup Lee
4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
Yunsup Lee
d6df479870
move 'include /Makefrag' out of top-level Makefrag
2015-07-14 16:13:32 -07:00
Henry Cook
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
Henry Cook
186e32a546
Merge pull request #9 from ucb-bar/param-based-makefrags
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Param-based makefrag generation
2015-07-13 15:51:28 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
Henry Cook
3573fcdf2d
bump uncore
2015-07-09 14:42:38 -07:00
Yunsup Lee
09e29e8fe0
add zscale
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only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba
New machine-mode timer facility
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Mirroring Andrew's commit to reference-chip
2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff
Added some multicore/multibanks named ChiselConfigs
2015-07-06 18:21:06 -07:00
Henry Cook
854fd64fba
Added optional Makefile includes for private chip repos
2015-07-06 17:15:27 -07:00
Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Scott Beamer
12d8d8c5e3
Merge pull request #8 from seldridge/master
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Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
2015-06-28 08:54:24 -05:00
Schuyler Eldridge
b4cd8c5981
Fix vlsi_mem_gen for Python 2 or 3
2015-06-25 12:48:31 -07:00
Schuyler Eldridge
a42832fc70
Fix fpga_mem_gen for Python 2 and 3 Environments
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Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00
Scott Beamer
a59ba39310
bump submodule for fpga-zynq
2015-05-21 11:26:57 -07:00
Scott Beamer
38edbc78e5
Merge pull request #5 from amsharifian/master
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Update Makefile
2015-05-21 11:24:25 -07:00
Amirali Sharifian
879a4a0bcd
Update Makefile
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Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
Yunsup Lee
4f57985198
change organization to riscv
2015-02-17 14:43:11 -08:00
Albert Magyar
09cd555f29
Update riscv-tools pointer to prepare for HPCA workshop.
2015-02-04 13:29:04 -08:00
Scott Beamer
2a5dd907f5
bump chisel version
2015-01-06 16:59:10 -08:00
Yunsup Lee
170f1fecbc
push chisel,rocket,riscv-tools
2014-10-21 12:32:58 -07:00
Yunsup Lee
1b31931981
Merge pull request #2 from wasserfuhr/patch-1
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Update README.md
2014-10-07 17:02:55 -07:00
