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Commit Graph

5234 Commits

Author SHA1 Message Date
Henry Cook
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
Howard Mao
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Howard Mao
000af5e662 add NastiIOHostIO converter test 2016-02-19 11:21:53 -08:00
Howard Mao
f97bd70df5 add NastiIO to HostIO converter 2016-02-19 11:21:23 -08:00
Howard Mao
fbd66ac87b expose a count in MultiWidthFifo 2016-02-19 11:20:43 -08:00
Howard Mao
5241ee6442 add multi-width FIFO 2016-02-19 11:20:43 -08:00
Palmer Dabbelt
926efd0cab Allow the number of memory channels to be picked at runtime
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
Palmer Dabbelt
95b065153d Add CDE to the submodule list
Without this I don't get rebuilds when toching a file in CDE.
2016-02-17 15:23:25 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Palmer Dabbelt
1ac9f59b31 Allow SCR files to be enumerated in C headers
Right now there's no way to ensure that SCR addresses don't conflict within
RocketChip.  Since upstream only has one of them this isn't a big deal, but we
want to add a whole bunch more to control all the IP on Hurricane.

This patch adds some Scala code to allocate registers inside the SCR file,
ensure they don't conflict, to provide names for SCRs, attach registers to the
SCR file, and generate a C header file that contains the addresses of every SCR
on a chip.

With this patch we'll be able to get rid of that constant in the testbench.
This also allows us to kill one of the Raven diffs, which is does pretty much
the same thing (just in a second SCR file, and hacked in).
2016-02-17 14:21:12 -08:00
Howard Mao
f290157cb3 check that MultiWidthFifo count is correct 2016-02-17 13:36:07 -08:00
Palmer Dabbelt
770f2742de Make NastiMemorySelector a subtype of NastiInterconnect
When RocketChip has a single memory configuration I want to ensure no extra
hardware is being generated by only instantiating a NastiMemoryInterconnect
rather than a NastiMemorySelector, which I believe will insert a Mux with 0
when there is only one config (because there aren't any 0-width wires allowed).
2016-02-17 10:41:01 -08:00
Palmer Dabbelt
6b39db8ce6 Add "NastiMemorySelector", a memory interconnect
On Hurricane we want to be able to support multiple memory channels but have a
fallback to fewer, since the full configuration is going to require a
complicated FPGA setup.  This adds another sort of interconnect that can switch
between having different numbers of top-level memory channels active at chip
boot time.

This interconnect is a bit funny: changing the select input when there is
memory traffic is a bad idea.  This is fine for this use case, since we really
only care about changing the memory configuration at boot time -- since it'll
scramble the memory of the machine it's not so useful, anyway.

The advantage is that we don't have to have a full 8x8 Nasti crossbar in our
chip, which would be fairly expensive.  Changing the crossbar would garble
memory as well, so it's not like it would add any extra functionality.
2016-02-16 23:59:01 -08:00
Howard Mao
4915a258f6 add unit test for some modules 2016-02-16 23:10:55 -08:00
Christopher Celio
8687ce5ebd bump torture 2016-02-16 15:13:59 -08:00
Christopher Celio
2e15d92d18 bump torture 2016-02-16 14:24:31 -08:00
Howard Mao
fef8a2d862 make sure NastiIOStreamIOConverter does not depend on external last signal 2016-02-15 09:48:35 -08:00
Christopher Celio
c1b4d9372f Revert "add new parameters for new SCR file"
This reverts commit 4dad5b8b32.

The commit breaks the build.
2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a Revert "use singleton for global"
This reverts commit 4d0f941de3.

The commit breaks the build.
2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3 use singleton for global 2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao
4b95374f0c bump rocket for bug fixes 2016-02-10 11:12:48 -08:00
Howard Mao
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Howard Mao
e90dfcb403 add test for NASTI to TL converter 2016-02-10 11:07:37 -08:00
Howard Mao
53ad8387cc add NASTI to TL converter 2016-02-10 11:06:52 -08:00
Howard Mao
2825b2d645 make sure TL to NASTI converter handles MT_WU 2016-02-10 11:06:41 -08:00
Christopher Celio
b96343a4e5 [btb] fix mix type error for fetch-width > 1
closes #24
2016-02-08 17:41:38 -08:00
Christopher Celio
31dd311aff [fpu] fix rounding mode bug in fdivfsqrt 2016-02-08 17:38:31 -08:00
Palmer Dabbelt
96b77f399c Merge pull request #43 from ucb-bar/chisel3
Bump junctions, for a chisel3 fix
2016-02-08 14:42:06 -08:00
Palmer Dabbelt
98baf401a6 Bump junctions, for a chisel3 fix 2016-02-08 13:33:05 -08:00
Andrew Waterman
b4856da819 Merge pull request #6 from ucb-bar/chisel3
Chisel 3 Support
2016-02-05 17:15:49 -08:00
Andrew Waterman
70945953a8 Merge pull request #42 from ucb-bar/chisel3
Chisel 3 support
2016-02-05 16:01:35 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
Palmer Dabbelt
62257e0b04 Uncomment MemSerializedIO.cloneType()
Not sure why this was commented, but when I build this against Chisel3 it fails
without this override.
2016-02-04 15:28:46 -08:00
Palmer Dabbelt
be424633c1 Improve ParamaterizedBundle.cloneType()'s error messages
Without this it's really hard to read the IllegalArgumentException that you get
if you subclass ParamaterizedBundle and don't define a matching cloneType().
2016-02-04 15:26:42 -08:00
Howard Mao
5abfd1a4ab make sure to check for region violations in DMA frontend 2016-02-03 15:40:44 -08:00
Colin Schmidt
c944193e16 add dma configs to travis 2016-02-02 16:06:01 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
2016-02-02 13:14:52 -08:00
Howard Mao
60d9291cb5 rename external to nastiExternal to avoid name conflicts 2016-02-02 13:14:04 -08:00
Howard Mao
bfdf5a538a Separate memory interconnect from IO interconnect.
Since we're separating memory and MMIO traffic in the L1 to L2 network,
we won't need to route between memory and MMIO at the AXI interconnect.
This means we can have separate (and simpler) AXI interconnects for
each. One consequence of this is that the starting address of the IO
interconnect can no longer be assumed to be 0 by default.
2016-02-02 13:14:04 -08:00
Howard Mao
66e9cc8c82 make sure CSR width is parameterizable 2016-02-02 12:49:58 -08:00
Howard Mao
adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao
c1fe188c81 some fixes to RTC 2016-02-02 12:49:58 -08:00
Howard Mao
ba94010928 DMA requests should go through MMIO 2016-02-02 12:49:58 -08:00
Palmer Dabbelt
97640f099d Merge pull request #41 from ucb-bar/regressions
Support torture regressions
2016-02-01 18:39:28 -08:00
Palmer Dabbelt
5cea4edee2 Bump riscv-tools for torture NaN ISA change 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e18759642f Avoid running Chisel in parallel in the same directory
It looks like Chisel fails when I try to run it in parallel.  This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
2016-01-31 23:06:59 -08:00