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On Hurricane we want to be able to support multiple memory channels but have a fallback to fewer, since the full configuration is going to require a complicated FPGA setup. This adds another sort of interconnect that can switch between having different numbers of top-level memory channels active at chip boot time. This interconnect is a bit funny: changing the select input when there is memory traffic is a bad idea. This is fine for this use case, since we really only care about changing the memory configuration at boot time -- since it'll scramble the memory of the machine it's not so useful, anyway. The advantage is that we don't have to have a full 8x8 Nasti crossbar in our chip, which would be fairly expensive. Changing the crossbar would garble memory as well, so it's not like it would add any extra functionality.