Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Henry Cook
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85e5ce046f
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pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
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Henry Cook
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784e017bae
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Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
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Henry Cook
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9b70ecf546
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Reg standardization
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2013-08-13 17:53:19 -07:00 |
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Henry Cook
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11e131af47
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initial attempt at upgrade
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2013-08-12 10:46:22 -07:00 |
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Henry Cook
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199e76fc77
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:31:27 -07:00 |
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Henry Cook
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4d916b56e3
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Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Henry Cook
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2796de01bf
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new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:41:27 -07:00 |
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Henry Cook
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c06cbf523b
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Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
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2013-05-23 15:26:20 -07:00 |
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Andrew Waterman
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d825c9d6e9
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make fpga Makefile work with updated Makefrag
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2013-05-02 05:09:45 -07:00 |
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Andrew Waterman
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cfa86dba4f
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add FPGA test bench
The memory models now support back pressure on the response.
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2013-05-02 04:59:32 -07:00 |
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Andrew Waterman
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50bd9a08a7
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resynchronize fpga uncore
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2013-05-01 01:12:47 -07:00 |
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Henry Cook
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eec590c1bf
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Added support for multiple L2 banks. Moved tile IO queueing.
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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806f897fc4
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-25 17:01:46 -07:00 |
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Andrew Waterman
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ce4c1aa566
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remove aborts
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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5b82d72eb7
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New TileLink bundle names
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2013-01-21 17:19:07 -08:00 |
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Henry Cook
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e33648532b
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Refactored packet headers/payloads
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2013-01-15 15:57:06 -08:00 |
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Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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