riscv/rocket-chip
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1405 Commits

Author SHA1 Message Date
Andrew Waterman
7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew Waterman
debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew Waterman
a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Megan Wachs
af6b2d8051 debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores. 2017-04-17 10:28:33 -07:00
Megan Wachs
b44d5f9386 debug: correctly consider .transfer bit in COMMAND 2017-04-17 10:28:33 -07:00
Megan Wachs
79477fbea6 debug: Properly consider 'transfer' bit 2017-04-17 10:28:33 -07:00
Megan Wachs
2dc4be6294 debug: remove preexec. Simplify the state machine since you can always just 'execute' once. 2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
7b8af96fc2 diplomacy: use circles for nodes again 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ae8fd0c60f graphML: don't draw unconnected LazyModules 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
fcf774f125 graphML: reverse interrupt arrows 2017-04-14 18:09:14 -07:00
Jacob Chang
d3925f0998 Add hooks to print debug information into the graphml file 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ba8be17c9a tilelink2: RAMModel, use CRC16 to check AMO response 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
6aeec673f2 util: add a CRC calculator 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
d794218ec3 tilelink2: RAMModel now checks atomic results 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
4f0ae1eab7 tilelink2: annotate which test generates RAMModel output 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
0b65fe9532 unittest: put AtomicAutomata under regression 2017-04-14 15:13:39 -07:00
Wesley W. Terpstra
248acbd1b4 tilelink2: add a generic TL2 atomic evaulation unit 2017-04-14 15:13:39 -07:00
Megan Wachs
fd7f4a4c0f jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
Andrew Waterman
34d45b4fb0 Fix whitespace error 2017-04-14 01:03:11 -07:00
Andrew Waterman
fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) 
* only replicate scratch slave d-channel resp when AMO req

* dtim: port can't support put partial mask with holes

* dtim: use \!isRead instead of isAMO

* Fix ScratchpadSlavePort looking at wrong Acquire message

Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
 2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf Unconditionally write badaddr, possibly to zero 
59d33f6b83
 2017-04-12 13:35:02 -07:00
Jim Lawson
907d369bde Remove tests obsoleted by new FP encoding proposal (#672) 2017-04-11 19:12:35 -07:00
Wesley W. Terpstra
1c36ab8bf7 Fragmenter: forbid multiple sink IDs 
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
 2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822 CacheCork: remove probe support 2017-04-11 12:34:18 -07:00
Andrew Waterman
9a983c12a3 Implement new FP encoding proposal 
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
 2017-04-10 22:38:25 -07:00
Andrew Waterman
470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Wesley W. Terpstra
71bf929505 maskgen: support wider granularity result (#665) 
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
 2017-04-09 20:06:23 -07:00
Andrew Waterman
a43bf2feae Add vectored interrupt support 
4dcaa944ba

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

ba6d88466a
 2017-04-08 00:29:45 -07:00
Megan Wachs
051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
Megan Wachs
9ae4838708 jtag: Get rid of chisel deprecation warnings 2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) 
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
 2017-04-06 10:33:17 -07:00
Andrew Waterman
c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
Megan Wachs
2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
solomatnikov
127f121ef2 Preserve id_do_fence (#651) 2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Megan Wachs
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Andrew Waterman
410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Henry Cook
b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Andrew Waterman
a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Megan Wachs
375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs
ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Andrew Waterman
8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Megan Wachs
d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
Megan Wachs
bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Megan Wachs
42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
 2017-03-27 21:19:08 -07:00
Megan Wachs
43804726ac tilelink2: more helpful requirement message 2017-03-27 21:05:05 -07:00
Megan Wachs
0c3d85b52b debug: add generated ROM contents and register fields. 2017-03-27 21:01:36 -07:00
Andrew Waterman
05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
a2a3346e73
 2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Megan Wachs
70fa10fc55 Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615) 2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Megan Wachs
11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice. 
This allows more flexibility e.g. considering the ROM as part of other
devices.
 2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. 2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be Add ucb-art/chisel-jtag (#612) 
* jtag: Add ucb-art/chisel-jtag to junctions.

* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch

* jtag: move to a top-level package
 2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10 Implement new FP encoding proposal 
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067 Fix groundtest to provide missing signals to TLB 2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
537274b645 coreplex: move buffers inside the coreplex 
This should make hierarchical place and route easier.
 2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078 rename l2FrontendBus as fsb, expose bsb 2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00