f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
c85e42a303
tilelink2: Nodes should accept full PortParameters
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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
5ff3d3d61c
correctly initialize with seed
2016-10-02 17:31:32 -07:00
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
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AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
8a268268ad
tilelink2 RegField: clarify restrictions on functions
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RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
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If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
e0188f8aa4
Don't implicitly fence on CSR instructions
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CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
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The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
784f0cf0b6
Merge pull request #370 from ucb-bar/move_clint_and_plic
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clint & plic: Move the default addresses
2016-10-01 16:18:54 -07:00
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
9a381e88d1
Suggest sane names for common objects ( #369 )
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* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
891a253bee
Merge pull request #367 from ucb-bar/tl2-isolation
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Tl2 isolation
2016-09-30 02:19:44 -07:00
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
a1fa0733e5
Merge pull request #366 from ucb-bar/slowio-change
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Change the configuration interface of SlowIO
2016-09-29 23:19:53 -07:00
4b86802b1a
change the configuration interface of SlowIO
2016-09-29 22:16:53 -07:00
8730887baa
Merge pull request #364 from ucb-bar/tl2-async-nodes
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Tl2 async nodes
2016-09-29 18:18:31 -07:00
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
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This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
ceb9c53c7d
Merge pull request #360 from ucb-bar/move-to-util
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Move a bunch more things into util package
2016-09-29 15:59:46 -07:00
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
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A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
e928b741ce
Default mtvec=0, not None
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Setting it to None was a mistake. It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
2016-09-29 13:52:41 -07:00
1e43512142
jtag: Actually apply the sticky bits
2016-09-29 13:49:34 -07:00
a4b81aebe0
jtag: Apply sticky bits for error and busy according to the current Debug Spec
2016-09-29 13:49:26 -07:00
fc4d6ed0c6
jtag: clean up debug flags in regression/Makefile
2016-09-29 13:49:21 -07:00
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
449d689a4e
jtag: Connect the JTAG DTM side of the synchronizer!
2016-09-29 13:48:55 -07:00
0924f8adb0
print out assigned inerrupt ranges
2016-09-29 11:59:32 -07:00
4c3e8ec1b4
assign interrupt ranges deterministically
2016-09-29 11:59:32 -07:00
4ac0ef2940
bump torture pointer after sim name change
2016-09-29 10:45:06 -07:00
7bca99a27a
[tilelink2] Add unit test configs to regression
2016-09-28 18:02:04 -07:00
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
69e121260e
[tilelink2] Add unit tests for many TL2 components
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These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
c45cc76cef
Get rid of remaining MemIO code
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The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
18e7ea89f2
Get rid of broken groundtests
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The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.
The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.
2016-09-27 16:28:17 -07:00
