adf5f1807b
tilelink2: ToAXI4 bridge added
2016-10-10 11:21:50 -07:00
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
2f7081aeaf
tilelink2: make mask generation reusable
2016-10-10 11:21:50 -07:00
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
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* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
c85e42a303
tilelink2: Nodes should accept full PortParameters
...
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
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AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
8a268268ad
tilelink2 RegField: clarify restrictions on functions
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RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
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If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
9a381e88d1
Suggest sane names for common objects ( #369 )
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* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
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This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
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A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
69e121260e
[tilelink2] Add unit tests for many TL2 components
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These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
f9e0a7ac24
Merge branch 'master' into async_register_crossing
2016-09-27 15:54:34 -07:00
eaea138d0d
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
f5502df6ab
Merge branch 'master' into async_register_crossing
2016-09-27 14:08:27 -07:00
357d06ac9c
tilelink2 WidthWidget: Gets must have their mask adjusted ( #353 )
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The mask of a Get should also be converted.
This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
2016-09-27 14:06:02 -07:00
3ce08f40a5
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
2016-09-27 13:36:28 -07:00
ea9f0a868f
TileLink utility objects should not take implicit parameters
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We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
d9e209365d
Tl2 addr width0 ( #346 )
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* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}
* tilelink2: use addr_lo instead of relying on truncation
Truncation can mess up if the width should be 0, but IS 1.
2016-09-26 17:00:03 -07:00
72c205b54f
tilelink2 AddressSet: add .misaligned(low, size) helper method ( #345 )
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This helps devices with misaligned ranges still connect to TL2.
2016-09-26 16:01:09 -07:00
1773eb4405
tilelink2 LazyModule: output GraphML of the bus
2016-09-26 14:35:46 -07:00
