Wesley W. Terpstra
9c0cc6fdf4
Merge pull request #537 from ucb-bar/l2-banks-together
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BankedL2Config: use the same LazyModule for all L2 banks
2017-01-30 15:39:04 -08:00
Wesley W. Terpstra
dc66c8857f
diplomacy: be more robust using Java introspection
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If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
2017-01-30 14:25:12 -08:00
Wesley W. Terpstra
280af9684b
BankedL2Config: use the same LazyModule for all L2 banks
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This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
2017-01-30 14:02:59 -08:00
Henry Cook
b567a2a356
Merge pull request #536 from ucb-bar/diplomacy-star-nodes
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diplomacy: add :*= and :=* to support flexible # of edges
2017-01-30 11:19:33 -08:00
Wesley W. Terpstra
f7f52cc722
diplomacy: restore Monitor functionality
2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c
uncore: switch to new diplomacy Node API
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Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
4d646939b0
diplomacy: make flexible-port adapters possible
2017-01-29 14:26:02 -08:00
Wesley W. Terpstra
24ee7f45f5
rocketchip: pass variable l1tol2 connections into coreplex
2017-01-29 11:18:36 -08:00
Wesley W. Terpstra
d5fa159063
diplomacy: add :*= and :=* to support flexible # of edges
2017-01-28 21:32:36 -08:00
Wesley W. Terpstra
03f2fe02ac
coreplex: support rational crossing to L2 ( #534 )
2017-01-27 17:09:43 -08:00
Richard Xia
61fbe62112
Ignore the built firrtl.jar. ( #532 )
2017-01-27 13:04:15 -08:00
Wesley W. Terpstra
19c58630d2
Merge pull request #533 from ucb-bar/rational-crossing
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Rational clock crossing
2017-01-26 22:30:04 -08:00
Wesley W. Terpstra
830d01329d
RationalCrossing: add some documentation
2017-01-26 21:27:34 -08:00
Wesley W. Terpstra
fc3b72084f
tilelink2: add a rational clock crossing adapter
2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
4b70386393
AsyncCrossing: disambiguate the file name
2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
5cf4b0632d
RationalCrossing: clock crossing between related clock domains
2017-01-26 20:07:28 -08:00
Jack Koenig
1285fa909f
Bump chisel and firrtl ( #531 )
2017-01-26 17:29:26 -08:00
Jim Lawson
3c1dac8c68
Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. ( #526 )
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This anticipates ucb-bar/chisel3#448 . When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.
2017-01-26 11:11:14 -08:00
Henry Cook
0fe2899c74
[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit ( #528 )
2017-01-25 12:10:49 -08:00
Wesley W. Terpstra
d1dedd25e7
Merge pull request #529 from ucb-bar/physical-optimization
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Physical optimization
2017-01-24 18:59:07 -08:00
Wesley W. Terpstra
6ff35a387a
tilelink2: disable A=>D bypass in ToAXI4 whenever possible
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
64e1de751d
axi4: add a minLatency parameter
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
46cdfc2b45
diplomacy: find names of LazyModules also in Seq() member values ( #527 )
2017-01-24 18:10:37 -08:00
Wesley W. Terpstra
3fc55298ef
coreplex: provide coherence managers with geometry information
2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
d4b3a0f0be
diplomacy: support given bits in AddressDecoder
2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
c0b6d31377
tilelink2: Delayer adapter useful for unit tests
2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
b3ef146805
Merge pull request #523 from ucb-bar/buffer-move
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coreplex: move TLBuffers for L2 and socBus
2017-01-21 14:53:51 -08:00
Wesley W. Terpstra
38c9ddffcc
BankedL2: move TLFilter BEFORE coherence manager
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This lets smart caches exclude the sets that are filtered.
2017-01-21 13:23:07 -08:00
Wesley W. Terpstra
dcadd5a006
coreplex: move TLBuffers for L2 and socBus
2017-01-20 22:23:36 -08:00
Wesley W. Terpstra
e8ce32a156
Merge pull request #515 from ucb-bar/cache-cork
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Cache cork
2017-01-19 20:00:51 -08:00
Wesley W. Terpstra
9dc7f180b6
diplomacy: support zero-port Nodes
2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
c0496fab29
regression: disable build that times out on Travis
2017-01-19 19:07:59 -08:00
Wesley W. Terpstra
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
3a5e5a65f8
coreplex: support multiple memory channels via diplomatic trickery
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
e7b35b4bb6
diplomacy: support multiple ports behind a BlindNode
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
258abc5629
coreplex: re-enable stateless L2 config
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
4bdb2e5d68
tilelink2 Monitor: ReleaseAck source does not count
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
fbf1073586
tilelink2: CacheCork - terminate caching
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
Henry Cook
e03ba637f4
[regression] remove FancyMemTest (timing out)
2017-01-19 17:48:04 -08:00
Henry Cook
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
Henry Cook
e0411c6cde
[coreplex] bugfix: re-enable multicore configs via WithNCores
2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
Megan Wachs
4fe75965a0
Merge pull request #518 from ucb-bar/dtm_regression
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jtag_dtm: Update regression to run and pass.
2017-01-18 14:39:53 -08:00
Megan Wachs
e22b01a6fa
jtag_dtm: Update regression to run and pass.
2017-01-18 12:08:13 -08:00
Henry Cook
1b31dfa700
Update sbt to 13.12 ( #514 )
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Closes #496
2017-01-17 16:26:22 -08:00
Henry Cook
9a6634cd40
Add TLBuffers on the L1 backends and blind exit points ( #513 )
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* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00
Henry Cook
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
Minux Ma
622e311962
Fix emulator argument processing for unknown DTM arguments ( #498 )
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Revision 7e79421
(issue #484 ) makes emulator.cc rejecting any unrecognized
+arg "legacy" arguments, however, this breaks riscv-torture emulator tests
as it needs to pass +signature to the DTM.
I think it is actually impossible to check for unknown argument here
unless we hardcode a list of all arguments recognized by fesrv. Fix this
issue by passing all arguments starting with the first unknown argument
to DTM.
Updates #484 .
Signed-off-by: Minux Ma <minux.ma@gmail.com>
2017-01-16 13:42:45 -08:00
GuzTech
8157cf1ede
Perform integer division when parsing rocketchip.DefaultConfig.conf ( #493 )
2017-01-13 16:40:02 -08:00