Wesley W. Terpstra
|
644f8fe974
|
rocketchip: switch to TL2 mmio + port PRCI
|
2016-09-15 21:28:56 -07:00 |
|
Wesley W. Terpstra
|
91e7da4de3
|
tilelink2: make RegisterRouter constructor args public
|
2016-09-15 21:28:56 -07:00 |
|
Wesley W. Terpstra
|
3875e11b26
|
tilelink2: RegField splits up big registers
|
2016-09-15 21:28:56 -07:00 |
|
Wesley W. Terpstra
|
5c8e52ca32
|
devices: TL2 version of ROM
|
2016-09-15 21:28:56 -07:00 |
|
Wesley W. Terpstra
|
3f30e11f16
|
tilelink2: Legacy, manager_xact_id does not matter for uncached
|
2016-09-15 21:28:55 -07:00 |
|
Wesley W. Terpstra
|
ddd93871d8
|
tilelink2: add an executable manager parameter
|
2016-09-15 21:28:55 -07:00 |
|
Wesley W. Terpstra
|
9442958d67
|
tilelink2: allow := on nodes outside the tilelink2 package
|
2016-09-15 21:28:55 -07:00 |
|
Jack Koenig
|
f2fe437fa4
|
Use CDEMatchError for improved performance (#304)
|
2016-09-15 19:47:18 -07:00 |
|
Henry Cook
|
851a336db4
|
[unittest] split out Config and TestHarness into separate files, minimize imports
|
2016-09-15 14:25:47 -07:00 |
|
Henry Cook
|
245f8ab76b
|
[util] move LatencyPipe into util
|
2016-09-15 13:30:34 -07:00 |
|
Henry Cook
|
a70d8c9821
|
Merge remote-tracking branch 'origin/master' into testharness-refactor
|
2016-09-15 13:27:07 -07:00 |
|
Henry Cook
|
be9ddae77f
|
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
|
2016-09-15 13:04:01 -07:00 |
|
Henry Cook
|
c6f252a913
|
Remove Option from success flag in coreplex; just use a sane default.
|
2016-09-15 12:19:22 -07:00 |
|
Henry Cook
|
9e2b0aad65
|
Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
|
2016-09-15 11:53:05 -07:00 |
|
Henry Cook
|
888f6a2a55
|
Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
|
2016-09-15 11:48:09 -07:00 |
|
Henry Cook
|
29ce599ea2
|
Merge pull request #295 from ucb-bar/tl2-irrevocable
TL2 -> IrrevocableIO
|
2016-09-15 11:33:05 -07:00 |
|
Henry Cook
|
0a65238920
|
Merge branch 'master' into tl2-irrevocable
|
2016-09-15 10:30:50 -07:00 |
|
Howard Mao
|
49863944c4
|
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
|
2016-09-14 21:36:27 -07:00 |
|
Howard Mao
|
f363f5f709
|
wrap TestHarness latency pipe in module
|
2016-09-14 21:16:54 -07:00 |
|
Howard Mao
|
f5db83a72f
|
NTiles should not be a Knob
|
2016-09-14 21:16:54 -07:00 |
|
Howard Mao
|
646527c88e
|
use named constants to set AXI resp, cache, and prot fields
|
2016-09-14 21:16:54 -07:00 |
|
Howard Mao
|
f95b8c4ec2
|
move UnitTest back into rocketchip module
|
2016-09-14 20:51:56 -07:00 |
|
Howard Mao
|
bf253aaa97
|
allow MODEL to be something other than TestHarness
|
2016-09-14 20:51:56 -07:00 |
|
Howard Mao
|
8550582f84
|
remove redundant verilator rule
|
2016-09-14 20:31:17 -07:00 |
|
jackkoenig
|
a304695ffd
|
Add firrtl and verilog Makefile targets to vsim
|
2016-09-14 20:29:59 -07:00 |
|
Henry Cook
|
cde104b3fa
|
[junctions] Removes the obsoleted SMI.
Closes #280.
|
2016-09-14 20:06:22 -07:00 |
|
Yunsup Lee
|
96110caca1
|
Merge pull request #291 from ucb-bar/move-bootrom
Move BootROM from Coreplex to Periphery
|
2016-09-14 19:51:16 -07:00 |
|
Henry Cook
|
ab3814dcee
|
Merge branch 'master' into tl2-irrevocable
|
2016-09-14 19:00:17 -07:00 |
|
Yunsup Lee
|
e404bea2ee
|
Merge branch 'master' into move-bootrom
|
2016-09-14 18:58:48 -07:00 |
|
Yunsup Lee
|
f2cb9da91a
|
Merge pull request #296 from ucb-bar/split-unittest
refactor unittest framework
|
2016-09-14 18:56:11 -07:00 |
|
Wesley W. Terpstra
|
1c7d7f9d32
|
tilelink2 RegisterRouterTest: stall on both edges
|
2016-09-14 18:22:12 -07:00 |
|
Yunsup Lee
|
97809b183f
|
refactor unittest framework
as a result, there's another SUITE that needs to run
|
2016-09-14 18:10:21 -07:00 |
|
Henry Cook
|
d35060b881
|
[junctions] messed up the merge lulz
|
2016-09-14 17:55:16 -07:00 |
|
Henry Cook
|
1b53e477fa
|
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
|
2016-09-14 17:50:17 -07:00 |
|
Henry Cook
|
e02d149cbe
|
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
|
2016-09-14 17:43:07 -07:00 |
|
Henry Cook
|
3030718f72
|
bump chisel3
|
2016-09-14 17:40:22 -07:00 |
|
Henry Cook
|
08c4c7b985
|
[junctions] make async crossings capable of providing IrrevocableIO
|
2016-09-14 17:38:54 -07:00 |
|
mwachs5
|
ae026edeb3
|
Merge pull request #293 from ucb-bar/async_clk_utils
Add some async/clock utilities
|
2016-09-14 16:59:27 -07:00 |
|
Megan Wachs
|
1308680f75
|
Add some async/clock utilities
|
2016-09-14 16:30:59 -07:00 |
|
Yunsup Lee
|
710f1ec020
|
Move BootROM from Coreplex to Periphery
|
2016-09-14 16:09:59 -07:00 |
|
Henry Cook
|
aa3fa90fe3
|
[tilelink2] Monitor: miscopied name in assert message
|
2016-09-14 14:56:50 -07:00 |
|
Henry Cook
|
d76e19a6ab
|
[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
|
2016-09-14 14:23:23 -07:00 |
|
Scott Beamer
|
f7121a2a5b
|
support for BSD sed (GNU sed still works)
|
2016-09-14 12:21:39 -07:00 |
|
Scott Beamer
|
cd12fd1cbb
|
fix clang support for emulator-debug
|
2016-09-14 12:20:37 -07:00 |
|
Andrew Waterman
|
565444c40e
|
Make UnitTestCoreplex cope with an external MMIO network
|
2016-09-14 12:19:21 -07:00 |
|
Andrew Waterman
|
2572cd3f7c
|
Add missing dependency
|
2016-09-14 11:50:28 -07:00 |
|
Andrew Waterman
|
5828e6042e
|
Work around https://github.com/ucb-bar/firrtl/issues/299
|
2016-09-14 11:47:10 -07:00 |
|
Andrew Waterman
|
c3ddff809b
|
Move PRCI from Coreplex to always-on block, where it belongs
|
2016-09-14 11:01:05 -07:00 |
|
Andrew Waterman
|
5566bf1b13
|
Don't route PLIC interrupts through PRCI
The PLIC is local to the Coreplex, and PRCI should not be.
|
2016-09-14 11:01:05 -07:00 |
|
Andrew Waterman
|
38b13da2f4
|
Bump chisel and firrtl
|
2016-09-14 11:01:05 -07:00 |
|