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Author	SHA1	Message	Date
Andrew Waterman	f1a506476b	Merge pull request #994 from freechipsproject/beu ... Add L1 bus-error unit	2017-09-20 12:17:08 -07:00
Henry Cook	00cf089350	Merge pull request #1002 from freechipsproject/trace ... Add instruction-trace port	2017-09-20 11:50:40 -07:00
Andrew Waterman	f5bd639863	Don't write badaddr on misaligned fetch exceptions ... It's optional, and we were doing it wrong before, so just don't do it.	2017-09-20 10:52:41 -07:00
Andrew Waterman	db57e943f3	Report TL errors into D$	2017-09-20 00:05:07 -07:00
Andrew Waterman	aaad73f019	Add an intra-tile xbar	2017-09-20 00:05:07 -07:00
Andrew Waterman	afad25fceb	Integrate L1 BusErrorUnit	2017-09-20 00:05:07 -07:00
Andrew Waterman	dbf599f6a1	Support SynchronizerShiftReg(sync = 0) ... This makes it easier to parameterize code where the synchronizer might not always be needed.	2017-09-20 00:05:07 -07:00
Andrew Waterman	79dab487fc	Implement bus error unit	2017-09-20 00:05:07 -07:00
Andrew Waterman	ed18acaae0	Report D$ errors	2017-09-20 00:05:07 -07:00
Andrew Waterman	034ea722f4	Report I$ errors	2017-09-20 00:05:07 -07:00
Andrew Waterman	9a175b0fb1	Statically report error correction/detection capability from ECC codes	2017-09-20 00:05:07 -07:00
Andrew Waterman	4d6d6ff641	Add instruction-trace port	2017-09-19 22:59:57 -07:00
Andrew Waterman	acea94bcef	Merge pull request #1001 from freechipsproject/address-decoder ... Address decoder "improvements"	2017-09-19 22:38:53 -07:00
Jacob Chang	b4fc5104d4	Add cover property API that can be refined through Config PropertyLibrary (#998)	2017-09-19 19:26:54 -07:00
Henry Cook	57e8fe0a6b	Merge pull request #1000 from freechipsproject/name-seqmems ... try to give seqmems clearer names for use with external tools	2017-09-19 17:59:00 -07:00
Andrew Waterman	87b92cb206	Scan AddressDecoder bits left to right ... This heuristic is brittle but fixes deduplication in RocketTile.	2017-09-19 17:47:24 -07:00
Andrew Waterman	72bd89a2af	Add another AddressDecoder debug message	2017-09-19 17:47:17 -07:00
Andrew Waterman	fb2ad11347	Improve AddressDecoder optimization function ... This function is better 27% of the time but worse 6% of the time.	2017-09-19 17:47:12 -07:00
Henry Cook	8db5bbbae0	try to give seqmems clearer names	2017-09-19 13:41:11 -07:00
Megan Wachs	cbd65cd247	Merge pull request #992 from freechipsproject/test_mode_reset ... reset_catch: Allow Test Mode Overrides	2017-09-18 14:16:49 -07:00
pbing	528deefdc7	Change SystemVerilog statement into standard Verilog (#997)	2017-09-18 10:57:07 -07:00
Megan Wachs	826fc8ba61	Merge remote-tracking branch 'origin/master' into test_mode_reset	2017-09-18 09:50:27 -07:00
Yunsup Lee	c24b275fd9	Merge pull request #996 from freechipsproject/fix-dcache-bug ... Only merge stores that aren't yet pending	2017-09-17 15:59:32 -07:00
Andrew Waterman	d93d7b9fa4	Only merge stores that aren't yet pending ... This fixes a deadlock (and possibly memory corruption, though that is unconfirmed). The following sequence manifests it, assuming t0 is 32-byte aligned: sw t0, 0(t0) sw t0, 16(t0) lw t1, 4(t0) lw t2, 4(t0)	2017-09-17 15:01:07 -07:00
Megan Wachs	c85333f826	Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset	2017-09-17 13:51:46 -07:00
Megan Wachs	215e072e5c	test_mode_reset: fix typos	2017-09-17 13:51:40 -07:00
Henry Cook	9b75dd7e5b	Merge branch 'master' into test_mode_reset	2017-09-15 17:26:11 -07:00
Megan Wachs	641a8e7eab	test_mode_reset: Correct some gender issues. Tie off signals in the test harness	2017-09-15 16:36:35 -07:00
Henry Cook	e8702e2687	Merge pull request #989 from freechipsproject/config-cleanups ... Clean up various Configs/Fields/Params	2017-09-15 13:45:15 -07:00
Megan Wachs	6cda4504ac	test_mode_reset: use a cleaner interface with bundles and options instead of individual signals	2017-09-15 12:30:39 -07:00
Megan Wachs	ffc514d1bc	test_mode_reset: Add missing file	2017-09-14 13:17:37 -07:00
Megan Wachs	a0396b63e8	test_mode_reset: fix one bulk-connect gender issue	2017-09-14 13:16:13 -07:00
Megan Wachs	44edc5fdc3	test_mode_reset: Use simpler apply() method	2017-09-14 13:16:13 -07:00
Megan Wachs	82c00cb656	reset_catch: Allow Test Mode Overrides	2017-09-14 13:16:13 -07:00
Henry Cook	e50d14415e	tilelink: more verbose requires	2017-09-13 11:25:42 -07:00
Henry Cook	56dae946b6	coreplex: MemoryBusParams.beatBytes also based on XLen	2017-09-13 11:25:42 -07:00
Henry Cook	b86f4b9bb7	config: use Field defaults over Config defaults ... Also rename some keys that had the same class name as their value's class name.	2017-09-13 11:25:42 -07:00
Henry Cook	a7540d35b7	ports: use BigInts instead of Longs and the new x"..." context	2017-09-13 11:25:42 -07:00
Henry Cook	37c5af1c0d	diplomacy: add x"..." string context ... Enables hex address literals containing underscores. Converts them to BigInts.	2017-09-13 11:25:42 -07:00
Henry Cook	063ca0ed4a	Merge pull request #983 from freechipsproject/kill-paddrbits ... Remove global fields PAddrBits and ResetVectorBits	2017-09-11 12:51:10 -07:00
Andrew Waterman	1f606d924f	Don't perform in-place correction if there was a recent store (#988) ... Since the correction updates the entire word, the WAW hazard detection logic is not sufficient to prevent overwriting a recent store. So, re-read the word after all pending stores have drained.	2017-09-08 16:26:54 -07:00
Henry Cook	9c0bfbd500	tile: remove global Field ResetVectorBits ... Reset vector width is determined by systemBus.busView. Also move some defs from HasCoreParameters to HasTileParameters.	2017-09-08 14:50:59 -07:00
Henry Cook	3133c321b7	scratchpad: remove dependency on HasCoreParameters	2017-09-08 13:55:40 -07:00
Henry Cook	e46aeb7342	tile: remove PAddrBits in favor of SharedMemoryTLEdge	2017-09-08 13:53:36 -07:00
Wesley W. Terpstra	e7de7f3e82	Merge pull request #985 from freechipsproject/flop-interrupts ... Add Parameters to diplomatic edges	2017-09-08 13:16:11 -07:00
Andrew Waterman	53dfc5e9be	Remove overzealous assertion (#987) ... This assertion made sure the D$ controller was able to write the tag RAM when a cache line was refilled. However, it is benign if it fails to do so: the metadata is invalid at this point, so the miss will simply happen a second time. This happens when resolving a tag ECC error during hit-under-miss.	2017-09-07 18:17:56 -07:00
Wesley W. Terpstra	e723a3f42b	MemoryBus: fanout the A for performance	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	6879f5bfb1	tilelink: Xbar now allows for fanout control	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	e831acba9c	adapters: support bulk connections	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	06a244f9f9	diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality	2017-09-07 16:03:35 -07:00