Henry Cook
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5075a93e6c
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util: dontTouch work-around for zero width aggregates
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2018-01-08 15:58:28 -08:00 |
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Henry Cook
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b77b93b0b4
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util: dontTouchPortsExcept
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2018-01-05 14:06:00 -08:00 |
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Jacob Chang
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ec3789b365
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Add Cross Cover Property Library (#1149)
Add cover points related to memory error to I/D Cache
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2017-12-07 18:46:10 -08:00 |
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Andrew Waterman
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efdb418559
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Merge pull request #1098 from freechipsproject/frontend
Frontend improvements
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2017-11-09 17:44:38 -08:00 |
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Wesley W. Terpstra
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4ccdbecb63
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Async covers (#1085)
* cover: support covering cross-product of ready-valid
* tilelink: AsyncCrossing now has covers for all flow control logic
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2017-11-01 11:03:45 -07:00 |
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Andrew Waterman
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a2b80100e2
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Make PseudoLRU policy support non-power-of-2 sizes
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2017-11-01 01:47:23 -07:00 |
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Wesley W. Terpstra
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2acff8d21f
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util: delete old long-deprecated crossing code
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2017-10-26 13:58:52 -07:00 |
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Wesley W. Terpstra
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5d62c321f4
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generator: create annotation file
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2017-10-10 23:23:06 -07:00 |
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Henry Cook
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75345b6048
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rocket: don't remove ports on top module
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2017-10-10 21:28:59 -07:00 |
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Henry Cook
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45581e60f0
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Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
This reverts commit 5232a29d7d , reversing
changes made to a2dc13669a .
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2017-10-05 00:26:44 -07:00 |
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Henry Cook
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d33737802a
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util: add DontTouch trait with dontTouchPorts method
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2017-10-02 19:36:34 -07:00 |
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Wesley W. Terpstra
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5323cf88dd
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util: add Option.unzip
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2017-09-25 12:06:31 -07:00 |
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Wesley W. Terpstra
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b9a2e4c243
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diplomacy: API beautification
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2017-09-22 15:01:42 -07:00 |
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Henry Cook
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e0b9f9213a
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make halt_and_catch_fire Optional
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2017-09-21 14:58:47 -07:00 |
|
Henry Cook
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28b635e721
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tile: add halt_and_catch_fire signal
for unrecoverable / fatal errors
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2017-09-21 14:58:47 -07:00 |
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Henry Cook
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a887baa615
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rocket: base trait for reporting ecc errors
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2017-09-21 14:58:47 -07:00 |
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Andrew Waterman
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dbf599f6a1
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Support SynchronizerShiftReg(sync = 0)
This makes it easier to parameterize code where the synchronizer
might not always be needed.
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2017-09-20 00:05:07 -07:00 |
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Andrew Waterman
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9a175b0fb1
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Statically report error correction/detection capability from ECC codes
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2017-09-20 00:05:07 -07:00 |
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Jacob Chang
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b4fc5104d4
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Add cover property API that can be refined through Config PropertyLibrary (#998)
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2017-09-19 19:26:54 -07:00 |
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Megan Wachs
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641a8e7eab
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test_mode_reset: Correct some gender issues. Tie off signals in the test harness
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2017-09-15 16:36:35 -07:00 |
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Megan Wachs
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6cda4504ac
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test_mode_reset: use a cleaner interface with bundles and options instead of individual signals
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2017-09-15 12:30:39 -07:00 |
|
Megan Wachs
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ffc514d1bc
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test_mode_reset: Add missing file
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2017-09-14 13:17:37 -07:00 |
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Megan Wachs
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82c00cb656
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reset_catch: Allow Test Mode Overrides
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2017-09-14 13:16:13 -07:00 |
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Wesley W. Terpstra
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5626cdd18f
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util: add the IdentityModule, useful to dedup wires
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2017-09-07 16:03:35 -07:00 |
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Wesley W. Terpstra
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2d93262f71
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RationalCrossing: use ShiftQueues
These are faster and small don't cost much more.
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2017-09-07 16:03:34 -07:00 |
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Wesley W. Terpstra
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50d5d8c1fd
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ShiftQueue: added a helper object
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2017-09-07 16:03:34 -07:00 |
|
Wesley W. Terpstra
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3e3024c256
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ShiftQueue: fix bug in !flow case
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2017-09-07 16:03:34 -07:00 |
|
Megan Wachs
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126d56b254
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synchronizers: I learn how foldRight works
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2017-09-07 10:48:27 -07:00 |
|
Megan Wachs
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1da6cb85ab
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shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
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2017-09-07 09:57:50 -07:00 |
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Megan Wachs
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3c4b472f66
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shift regs: remove some unnecessary primitives, and add some that actually are necessary
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2017-09-06 10:37:59 -07:00 |
|
Megan Wachs
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777f052f95
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regs: Add named/initial value ShiftRegister primitives so they are all in one place
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2017-09-05 17:32:53 -07:00 |
|
Megan Wachs
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e9e46db600
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sync reg: Rename the file to reflect the more generic shift registers also in the file.
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2017-09-05 15:54:25 -07:00 |
|
Megan Wachs
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5df23c5514
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Synchronizers: remove some newlines and unncessary gen's
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2017-09-05 15:17:21 -07:00 |
|
Megan Wachs
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a3bc5f2e33
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synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
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2017-08-30 12:59:16 -07:00 |
|
Megan Wachs
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8139014c9e
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syncrhonizers: Remove unused sync from superclass
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2017-08-30 12:33:03 -07:00 |
|
Megan Wachs
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9dd6c4c32d
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synchronizers: New chisel ways of cloning type and use simpler lambda function
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2017-08-30 12:11:14 -07:00 |
|
Megan Wachs
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bd32f0c122
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synchronizers: properly pass parameters up to the superclass
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2017-08-30 11:58:25 -07:00 |
|
Megan Wachs
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483e63da19
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synchronizers: Correctly pass the width through
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2017-08-30 11:50:25 -07:00 |
|
Megan Wachs
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451334ac73
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Add 1-deep synchronizer register for output of AsyncQueue
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2017-08-28 17:18:54 -07:00 |
|
Megan Wachs
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85c39b2f97
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syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
|
2017-08-24 17:47:04 -07:00 |
|
Megan Wachs
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4e773f4738
|
syncregs: Use synchronizer primivites for LevelSyncCrossing
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2017-08-24 17:42:31 -07:00 |
|
Megan Wachs
|
8b462d1595
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syncregs: Use common primitives for AsyncQueue grey code synchronizers
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2017-08-24 17:34:07 -07:00 |
|
Megan Wachs
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3461cb47cc
|
syncregs: Make Reset catcher use the synchronizer primitive
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2017-08-24 17:26:38 -07:00 |
|
Megan Wachs
|
c78ee9f0e4
|
syncreg: Refactor common code
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2017-08-24 17:18:04 -07:00 |
|
Megan Wachs
|
d83a6dc6af
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syncregs: Add utilities for Synchronizing Shift Registers
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2017-08-24 16:55:17 -07:00 |
|
Megan Wachs
|
7f683eeb24
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async_regs: Make modules have predictable names
|
2017-08-24 15:33:53 -07:00 |
|
Megan Wachs
|
0f75ebee92
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async_reg: Rename the file to match scalastyle
|
2017-08-24 15:31:29 -07:00 |
|
Wesley W. Terpstra
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710a782145
|
HeterogenousBag: empty bags were being combined! (#956)
This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
|
2017-08-14 15:48:42 -07:00 |
|
Andrew Waterman
|
bc298bf146
|
Optimize ShiftQueue for late-arriving deq.ready
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2017-08-04 22:06:37 -07:00 |
|
Yunsup Lee
|
6ef8ee5d4d
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tilelink: add mask rom
|
2017-07-31 21:34:04 -07:00 |
|