Wesley W. Terpstra
748a48f667
unittest: balance the run times of the tests
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
bea2489507
unittest: make overall test duration configurable
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
c8ba6b2feb
unittests: accept a configurable number of transactions to run
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442
unit tests: all should accept timeout override
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
4acc302158
unittest: disable XBar test from regression (covered by other tests)
2017-05-17 14:02:59 -07:00
Colin Schmidt
0c382204d4
give them all stages
2017-05-17 12:38:52 -07:00
Colin Schmidt
62a54e6bdb
inline the env matrix
2017-05-17 12:36:49 -07:00
Colin Schmidt
2f3e22aff6
matrix outside after jobs
2017-05-17 12:34:11 -07:00
Colin Schmidt
f3775cbbbf
try moving matrix into jobs
2017-05-17 12:31:13 -07:00
Henry Cook
dfabf68d9c
Merge pull request #746 from freechipsproject/fix-bundle-refs
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diplomacy: provide connect access to edges without bundles
2017-05-17 12:28:46 -07:00
Colin Schmidt
b7dc415522
maybe this will order them with deploy last
2017-05-17 12:28:01 -07:00
Colin Schmidt
b9fc169367
try another stages organization
2017-05-17 12:24:41 -07:00
Colin Schmidt
83a5230e91
change install to script?
2017-05-17 12:13:31 -07:00
Colin Schmidt
bce613ce38
try using a new travis staging feature
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The idea is to let us avoid building the tools
for each SUITE
2017-05-17 11:58:09 -07:00
Wesley W. Terpstra
8c3736e0dc
tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer
2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3
diplomacy: appease Jack by removing unused 1st bundles argument
2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2
tilelink2: don't widen TLMonitor interface unnecessarily
2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800
diplomacy: provide connect access to edges without bundles
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Forcing the bundles to exist early can mess up module ownership.
2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
65053978dc
Merge pull request #745 from freechipsproject/tile-xbar
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Tile xbar
2017-05-17 06:28:37 -07:00
Megan Wachs
d8996ea85f
Empty commit to force travis
2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f
rocc: fix RoccExampleConfig
2017-05-16 16:44:53 -07:00
Henry Cook
a19fc2549e
tile: add tileBus xbar
2017-05-16 16:12:01 -07:00
Wesley W. Terpstra
ad087dd18d
Merge pull request #742 from ucb-bar/true-rational
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RationalCrossing: now supporting true rational N:M crossings
2017-05-15 15:51:35 -07:00
Wesley W. Terpstra
3e2b477c0a
rational: adjust comments and add a case for N:M
2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
2119df5a60
vsrc: add ClockDivider3 used to simulate unaligned clocks
2017-05-14 15:05:55 -07:00
Wesley W. Terpstra
05e7501e7a
build: include chiselName and give an example of using it ( #738 )
2017-05-12 06:25:58 -07:00
Wesley W. Terpstra
18725a05b0
DTS tweaks ( #740 )
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* rocket: do not report 's' in isa string
* rocket: report the micro-architecture of the core
2017-05-12 05:32:57 -07:00
Jack Koenig
a69fcd50dd
Bump Firrtl to add new global DCE ( #741 )
2017-05-12 00:36:49 -07:00
Palmer Dabbelt
23706113c2
Bump riscv-tools, to get some -mcmodel=medany fixes ( #739 )
2017-05-11 21:04:32 -07:00
Henry Cook
5f3a4ada1b
diplomacy: add legalize method to AddressSet
2017-05-10 12:54:24 -07:00
Henry Cook
3af40bff8b
tilelink: better address masking for fuzzing
2017-05-10 12:54:24 -07:00
Wesley W. Terpstra
9720a53eae
Merge pull request #735 from ucb-bar/early-ack-frag-fix
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tilelink2: keep earlyAck Fragmenter sources distinct
2017-05-09 18:22:59 -07:00
Wesley W. Terpstra
3eaa973da7
tilelink2: add earlyAck to regression
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
3e7bdcbf5e
tilelink2: Fragmenter should ignore error when not valid
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e
tilelink2: keep earlyAck Fragmenter sources distinct
2017-05-09 17:35:22 -07:00
Palmer Dabbelt
19db0389b6
Merge pull request #732 from ucb-bar/vectored-stvec
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Support vectored stvec interrupts, too
2017-05-09 09:34:47 -07:00
Andrew Waterman
3a9bbd7e58
Merge branch 'master' into vectored-stvec
2017-05-08 14:08:09 -07:00
Wesley W. Terpstra
fd76f45f65
Merge pull request #731 from ucb-bar/axi-zero-width
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axi4: Support AXI4-Lite properly
2017-05-08 10:48:32 -07:00
Wesley W. Terpstra
2d8a49cc06
tilelink2: Fragmenter client must request global FIFO
2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1
axi4: Test AXI4-Lite in regression
2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845
axi4: SRAM support 0 userBits
2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86
axi4: Deinterleaver must gather R also for single ID
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In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2
axi4: IdIndexer; a single ID does NOT imply no response interleaving
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Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599
tilelink: ToAXI4 - must interlock till last beat
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AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411
axi4: IdIndexer now handles 0-width IDs
2017-05-08 00:17:02 -07:00
Andrew Waterman
7eefc12705
Support vectored stvec interrupts, too
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137812654e
2017-05-07 15:40:08 -07:00
Andrew Waterman
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
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This reverts commit ea0714bfcb326bec83de
2017-05-07 15:23:21 -07:00
Andrew Waterman
dd1546fd69
Check PPN LSBs for superpage PTEs
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5a32fe8782
2017-05-05 15:30:09 -07:00
Yunsup Lee
431e726c29
Merge pull request #727 from ucb-bar/fix-axi2tl-timeout
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Wes's fix for AXI2TL timeout when writes backed up
2017-05-04 01:42:48 -07:00
Scott Johnson
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
