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Author SHA1 Message Date
Andrew WatermanandAndrew Waterman 34d45b4fb0 Fix whitespace error 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman 6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman b9e042d2bf Unconditionally write badaddr, possibly to zero 
https://github.com/riscv/riscv-isa-manual/commit/59d33f6b833d6499edfa825a204933098345d53d
 2017-04-12 13:35:02 -07:00
Andrew WatermanandAndrew Waterman 9a983c12a3 Implement new FP encoding proposal 
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman 470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman a43bf2feae Add vectored interrupt support 
https://github.com/riscv/riscv-isa-manual/commit/4dcaa944ba40e074d25516a157fc37f7491b71cc

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

https://github.com/riscv/riscv-tests/commit/ba6d88466a96ec3147b96a57f746a137085764f9
 2017-04-08 00:29:45 -07:00
Andrew WatermanandAndrew Waterman 5c458322b5 bump chisel for withReset bugfix 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
Andrew WatermanandAndrew Waterman 19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Andrew WatermanandAndrew Waterman 410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Andrew Waterman a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman 2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman 70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Andrew Waterman fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Andrew Waterman 3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman 8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman 25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman 80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Andrew WatermanandAndrew Waterman 44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew WatermanandAndrew Waterman db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew WatermanandAndrew Waterman 4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Andrew Waterman 05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman 069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
https://github.com/riscv/riscv-isa-manual/commit/a2a3346e7345619efe3b5e8620d4a87c72d21ad0
 2017-03-27 16:37:09 -07:00
Andrew WatermanandAndrew Waterman 0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman e710e32f10 Implement new FP encoding proposal 
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman 7180352067 Fix groundtest to provide missing signals to TLB 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman 5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Andrew Waterman 17b1ee3037 Default to 8 PMPs; support 0 PMPs 2017-03-24 16:39:52 -07:00
Andrew Waterman 97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM 2017-03-24 16:39:52 -07:00
Andrew Waterman 3f0d2fe826 Instantiate PTW unconditionally 
This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses 2017-03-24 16:39:52 -07:00
Andrew Waterman ccd5bc9a91 Improve QoR of PMP homogeneity checker 2017-03-24 16:39:52 -07:00
Andrew Waterman 0182b6ca07 bump tools 2017-03-24 16:39:52 -07:00
Andrew Waterman e9cadf29d2 Improve DCache MMIO QoR 
No need to store the cmd field.  From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
 2017-03-24 16:39:52 -07:00
Andrew Waterman fb6498f2c3 Use Reg(Vec) instead of Seq(Reg) for DCache MMIO 2017-03-24 16:39:52 -07:00
Andrew Waterman 0538dc77ce For D$, use source 0 through N-1 for MMIO, not 1 through N 
This makes the code a bit cleaner.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 3951e57789 Force each TLB entry into its own clock-gate group 
This ameliorates a PMP critical path.

I can't figure out how to do this without asUInt/asTypeOf.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 8d7f1d777e Fix an embarrassing typo in the PMPHeterogeneityChecker 2017-03-24 16:39:52 -07:00
Andrew Waterman 10c39cb8d6 Disable mprv in D-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman d3bda9574c Put page homogeneity checker in PMP 
Avoids redundancy between ITLB and DTLB
 2017-03-24 16:39:52 -07:00
Andrew Waterman 9e05200e51 Don't require that PMP ranges be aligned to access size 
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 29e67279ba add comments 2017-03-24 16:39:52 -07:00
Andrew Waterman 4c8be13a4d Improve homogeneity circuit QoR 2017-03-24 16:39:52 -07:00
Andrew Waterman 59d6afa132 mideleg/medeleg not present without less-privileged traps 2017-03-24 16:39:52 -07:00
Andrew Waterman 38808f55d5 Share PMP mask gen between I$ and D$ 2017-03-24 16:39:52 -07:00
Andrew Waterman 86d84959cf More WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman 2888779422 Flush pipeline from WB stage, not MEM 
Fixes sptbr write -> instruction translation hazard.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 44ca3b60ab Retime PTW response valid bits 
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
 2017-03-24 16:39:52 -07:00
Andrew Waterman a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Andrew Waterman 1875407316 Get TLB permission checks off D$ clock gating critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman a4164348b4 Expose MXR to S-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman 0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman 2a413e4496 Remove fruitless debug() 2017-03-24 16:39:52 -07:00
Andrew Waterman 29414f3a23 Simplify interrupt-stack discipline 
https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542
 2017-03-24 16:39:52 -07:00
Andrew Waterman 723352c3e2 Mitigate some more PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman 7484f27ed3 Don't gate exception-cause pipeline registers separately 
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
 2017-03-24 16:39:52 -07:00
Andrew Waterman 3ea822c2cf Make blocking L1 D$ the default 
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 487b8db5ef Address some PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman 03fb334c4c Take mprv calculation off critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman f0796f0509 Pass correct access size information to PMP checker 2017-03-24 16:39:52 -07:00
Andrew Waterman a6874c03f7 Remove DecoupledTLB 2017-03-24 16:39:52 -07:00
Andrew Waterman 78f9f6b9ef When SFENCE.VMA has rs2 != x0, don't flush global mappings 2017-03-24 16:39:52 -07:00
Andrew Waterman 1b950128e1 PTW should always use S-mode privilege 
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode.  However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.

Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
 2017-03-24 16:39:52 -07:00
Andrew Waterman aace526857 WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman b1b405404d Set PRV=M when entering debug mode 
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
 2017-03-24 16:39:52 -07:00
Andrew Waterman cf168e419b Support SFENCE.VMA rs1 argument 
This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 76f083b469 FIFOFixer: Not all D-channel messages are A-channel responses 2017-03-21 14:17:38 -07:00
Andrew Waterman 3609254e4a There's no structural hazard on MMIO store responses 
So don't stall as though there were.
 2017-03-21 14:17:32 -07:00
Andrew Waterman d6f571cbbb Implement mstatus.TSR 2017-03-13 14:50:06 -07:00
Andrew Waterman 1fea0460ba Support superpage entries in TLB 2017-03-13 14:50:06 -07:00
Andrew Waterman 2d267b4940 Support corner cases in TLBPermissions 
Don't crap out if the yes-set or no-set is empty.
 2017-03-13 14:50:06 -07:00
Andrew Waterman 90b5cc96cb Gracefully handle empty ports in AddressDecoder 2017-03-13 14:50:06 -07:00
Andrew Waterman 380c10f7bd Zap conflicting TLB entries, preparing for superpage support 
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation.  This
isn't compatible with the Mux1H approach.  So, flush the TLB and report
a miss on duplicate entries.
 2017-03-10 15:58:23 -08:00
Andrew Waterman b24c43badb Don't double-count release traffic in perfctrs 2017-03-09 16:49:02 -08:00
Andrew Waterman 63f8ce36f6 Avoid VM exceptions in groundtest by setting Accessed bit 2017-03-09 16:48:28 -08:00
Andrew Waterman 4f8f05d635 Add performance counter facility 2017-03-09 13:58:50 -08:00
Andrew Waterman e57ee2692d bump tools 2017-03-09 13:58:40 -08:00
Andrew Waterman 33b6d48376 Fix haltnot reporting (previously always returned 0) 2017-03-09 13:58:40 -08:00
Andrew Waterman 24a2278fc4 Perform all illegal-instruction detection in ID stage 
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 7668827741 Support unrolling the integer divider 2017-03-09 11:29:51 -08:00
Andrew Waterman 74d8d672bf Improve BTB critical path at slight accuracy cost 
Make entries fully associative on lower 14 bits only, not full address.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Andrew Waterman db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Andrew WatermanandAndrew Waterman 603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines 
It's redundant with the new scheme, so just adds HW for no reason.
 2017-03-07 20:51:32 -08:00
Andrew WatermanandAndrew Waterman f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew WatermanandAndrew Waterman cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result 
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
 2017-03-07 20:51:32 -08:00
Andrew Waterman dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Andrew WatermanandAndrew Waterman 8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN 
See https://github.com/riscv/riscv-isa-sim/issues/76
 2017-02-02 11:55:08 -08:00
Andrew WatermanandAndrew Waterman 75edf42323 Set xPIE=1 on xRET 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
 2017-02-02 11:55:08 -08:00
Andrew WatermanandHenry Cook f1cb06142e bump tools 2017-01-11 13:21:55 -08:00