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Author SHA1 Message Date
Megan Wachs
76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Megan Wachs
237689b799 Merge pull request #838 from freechipsproject/more_plic 
plic: Use same recoding technique on complete as well as claim
 2017-06-30 11:06:27 -07:00
Wesley W. Terpstra
367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Jack Koenig
8d07d0af38 Merge pull request #820 from freechipsproject/bump-firrtl 
Bump firrtl to get constant propagation improvements
 2017-06-26 18:47:50 -07:00
Wesley W. Terpstra
66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Jack
e461e0f796 Bump firrtl to get constant propagation improvements 2017-06-26 17:18:52 -07:00
Andrew Waterman
72c46e6c05 Merge pull request #818 from sashimi-yzh/faster-verilator-compile 
emulator,Makefile-verilator: add --output-split-cfuncs flag
 2017-06-26 11:39:42 -07:00
Zihao Yu
fc85a3ce02 emulator,Makefile-verilator: add --output-split-cfuncs flag 
* Originally verilator will generate a large cpp file containing a large
  function, which costs about 13 min to compile. By using --output-split-cfuncs,
  this large function will be splitted into several functions in servral
  files. This will greatly improve the compile time with 'make -j'. By '-j32',
  the compile time can be reduced to about 1 min.
 2017-06-26 14:29:29 +08:00
Wesley W. Terpstra
7a0655ae88 Merge pull request #816 from freechipsproject/reduce-axi-queues 
Reduce AXI4 queues
 2017-06-23 18:31:41 -07:00
Wesley W. Terpstra
8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits 
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
 2017-06-23 17:22:45 -07:00
Wesley W. Terpstra
feecfb53ed axi4: Deinterleaver need not make a Q for an unused AXI id 2017-06-23 17:22:42 -07:00
Wesley W. Terpstra
9bea7c1c58 Merge pull request #815 from freechipsproject/reduce-others 
Reduce others
 2017-06-23 12:13:48 -07:00
Wesley W. Terpstra
2d8b2f4edd ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
Henry Cook
ad4b454b49 isp: passthru based on edgesOut = edgesIn (#814) 2017-06-22 21:23:49 -07:00
Wesley W. Terpstra
48611266fa diplomacy: use ReduceOthers in the RegMapper 2017-06-22 19:43:47 -07:00
Wesley W. Terpstra
11d1cb02eb util ReduceOthers produces nlogn cost ready-valid logic 2017-06-22 19:43:20 -07:00
Scott Johnson
1f18a37f01 Merge pull request #813 from freechipsproject/scottj97-patch-1 
Update Readme: rocket-chip uses Travis, not Jenkins
 2017-06-22 13:33:15 -07:00
Jack Koenig
1f137cb9ff Merge pull request #800 from ss2783/patch-1 
GeneratorUtils: support to elaborate a RawModule
 2017-06-22 12:34:41 -07:00
Colin Schmidt
aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
 2017-06-22 12:07:09 -07:00
Scott Johnson
bd803d278a Update Readme: rocket-chip uses Travis, not Jenkins 2017-06-22 10:16:10 -07:00
Scott Johnson
f1130b2faf Merge pull request #812 from freechipsproject/bump-tools 
Bump riscv-tools to get new riscv-isa-sim
 2017-06-22 08:40:00 -07:00
Scott Johnson
a7273bccbe Bump riscv-tools to get new riscv-isa-sim 2017-06-21 22:34:25 -07:00
Henry Cook
0fdaa28694 Merge pull request #811 from freechipsproject/isp-tweaks 
Assorted changes based on ISP use cases
 2017-06-20 19:24:28 -07:00
Henry Cook
bf431c0a53 groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
Wesley W. Terpstra
2f2fe0a973 clint: don't ask for what you know (nTiles) 2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names 2017-06-20 17:18:45 -07:00
Henry Cook
5552f23294 tims: explictly name them for generated address map 2017-06-20 17:18:29 -07:00
Henry Cook
6b79842e66 dcache: just left shift by untagbits to get tag 
Always safe because of the requirement on coreplex/RocketTiles.scala:126
 2017-06-20 16:35:28 -07:00
Henry Cook
7521050a48 Merge pull request #810 from freechipsproject/isp-fixes 
ISP fixes
 2017-06-20 16:35:06 -07:00
Wesley W. Terpstra
bb309e573f TLSplitter: special-case the case of no split necessary 2017-06-20 14:10:25 -07:00
Wesley W. Terpstra
53f030c037 TLSplitter: default policy is roundRobin 
Track commit 274d908d98
 2017-06-20 14:03:01 -07:00
Wesley W. Terpstra
1aa4f5ce33 TLSplitter: QoR improvements 
Track commit 985d9750e6
 2017-06-20 14:01:07 -07:00
Wesley W. Terpstra
f6e0dd12c8 TLSplitter: ManagerUnification is not used in Xbars 
Track the change made in 5994714970
 2017-06-20 13:58:30 -07:00
Andrew Waterman
f396b4142d Merge pull request #806 from freechipsproject/mulh 
Improve integer mul/div
 2017-06-20 13:01:16 -07:00
Colin Schmidt
675f183dd2 refactor ICache to be reusable by other frontends (#808) 
* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction
 2017-06-20 08:21:01 -07:00
Andrew Waterman
a6d9884cc0 Improve integer mul/div 
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
 2017-06-19 12:09:21 -07:00
Shreesha Srinath
ff1f0170dc changing SystemVerilog params to Verilog style (#801) 
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
 2017-06-16 22:47:12 -07:00
Richard Xia
31415060fe Merge pull request #802 from freechipsproject/fix-decode-of-instruction-after-ebreak 
Check for rvc before declaring illegal instruction after an ebreak.
 2017-06-16 15:07:24 -07:00
Richard Xia
61c39da475 Check for rvc before declaring illegal instruction after an ebreak. 2017-06-16 10:49:36 -07:00
Megan Wachs
d0f8cdd00c Merge pull request #804 from freechipsproject/travis_cache_stages 
travis: attempt to make 2 build stages for cache
 2017-06-16 07:31:56 -07:00
Wesley W. Terpstra
a89c0551b7 travis: use travis_wait again 
Timeouts due to inactivity again :-/
 2017-06-15 23:04:17 -07:00
Megan Wachs
30a3e3ef55 travis: attempt to make 2 build stages for cache 
First stage builds riscv-tools, next stage builds verilator
 2017-06-15 21:31:15 -07:00
Wesley W. Terpstra
93d423d202 diplomacy: optimize IdRange.contains (#798) 
This should make an optimal circuit for a wider class of ranges.
 2017-06-15 15:56:14 -07:00