Wesley W. Terpstra
943c36954d
tilelink2 RegField: .bytes should update more than one byte!
2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4
Fix deprecation warnings
2016-09-16 14:24:19 -07:00
mwachs5
a031686763
util: Do BlackBox Async Set/Reset Registers more properly ( #305 )
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* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d
Simplify AsyncResetRegVec and make AsyncResetReg companion object
2016-09-16 11:25:10 -07:00
Yunsup Lee
198a2d7022
Merge pull request #302 from ucb-bar/tl2-mmio
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Tl2 mmio
2016-09-15 22:45:35 -07:00
Wesley W. Terpstra
dd19e0911e
tilelink2: handle bus width=1
2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df
PRCI: always use bus width >= XLen
2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
2c53620275
chisel3: bump for Irrevocable(Decoupled) constructor
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
0e80f7fd0f
HintHandler: don't violate Irrevocable rules
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75
Comparator: don't compare addr_beat when it's irrelevant
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956
RegisterRouter: compress register mapping for sparse devices
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc
tilelink2: compute minimal decisive mask
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3
tilelink2: make RegisterRouter constructor args public
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26
tilelink2: RegField splits up big registers
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32
devices: TL2 version of ROM
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16
tilelink2: Legacy, manager_xact_id does not matter for uncached
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8
tilelink2: add an executable manager parameter
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67
tilelink2: allow := on nodes outside the tilelink2 package
2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
Henry Cook
851a336db4
[unittest] split out Config and TestHarness into separate files, minimize imports
2016-09-15 14:25:47 -07:00
Henry Cook
245f8ab76b
[util] move LatencyPipe into util
2016-09-15 13:30:34 -07:00
Henry Cook
a70d8c9821
Merge remote-tracking branch 'origin/master' into testharness-refactor
2016-09-15 13:27:07 -07:00
Henry Cook
be9ddae77f
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913
Remove Option from success flag in coreplex; just use a sane default.
2016-09-15 12:19:22 -07:00
Henry Cook
9e2b0aad65
Revert "allow MODEL to be something other than TestHarness"
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This reverts commit bf253aaa97
2016-09-15 11:53:05 -07:00
Henry Cook
888f6a2a55
Revert "move UnitTest back into rocketchip module"
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This reverts commit f95b8c4ec2
2016-09-15 11:48:09 -07:00
Henry Cook
29ce599ea2
Merge pull request #295 from ucb-bar/tl2-irrevocable
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TL2 -> IrrevocableIO
2016-09-15 11:33:05 -07:00
Henry Cook
0a65238920
Merge branch 'master' into tl2-irrevocable
2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709
wrap TestHarness latency pipe in module
2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f
NTiles should not be a Knob
2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e
use named constants to set AXI resp, cache, and prot fields
2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2
move UnitTest back into rocketchip module
2016-09-14 20:51:56 -07:00
Howard Mao
bf253aaa97
allow MODEL to be something other than TestHarness
2016-09-14 20:51:56 -07:00
Howard Mao
8550582f84
remove redundant verilator rule
2016-09-14 20:31:17 -07:00
jackkoenig
a304695ffd
Add firrtl and verilog Makefile targets to vsim
2016-09-14 20:29:59 -07:00
Henry Cook
cde104b3fa
[junctions] Removes the obsoleted SMI.
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Closes #280 .
2016-09-14 20:06:22 -07:00
Yunsup Lee
96110caca1
Merge pull request #291 from ucb-bar/move-bootrom
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Move BootROM from Coreplex to Periphery
2016-09-14 19:51:16 -07:00
Henry Cook
ab3814dcee
Merge branch 'master' into tl2-irrevocable
2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee
Merge branch 'master' into move-bootrom
2016-09-14 18:58:48 -07:00
Yunsup Lee
f2cb9da91a
Merge pull request #296 from ucb-bar/split-unittest
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refactor unittest framework
2016-09-14 18:56:11 -07:00
Wesley W. Terpstra
1c7d7f9d32
tilelink2 RegisterRouterTest: stall on both edges
2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f
refactor unittest framework
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as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881
[junctions] messed up the merge lulz
2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
2016-09-14 17:43:07 -07:00
