riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity
524 Commits 1 Branch 0 Tags 13 MiB
Commit Graph

524 Commits

Author SHA1 Message Date
Colin Schmidt 7259239ba4 Merge pull request #31 from ucb-bar/multirocc 
implement support for multiple RoCC accelerators
 2015-11-28 08:56:07 -05:00
Howard Mao 23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Andrew Waterman e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Andrew Waterman 49d93da87e Factor out more common zscale code 2015-11-24 19:17:21 -08:00
Andrew Waterman 52b25c3da0 Factor out more common zscale code 2015-11-24 18:34:03 -08:00
Andrew Waterman 1761db3272 Factor out some common code from zscale 2015-11-24 18:14:06 -08:00
Howard Mao ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao 9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao 4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao 3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao 379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Yunsup Lee ea8ba49805 improve memory system: specialize MultiChannel routing 2015-11-18 21:58:22 -08:00
Andrew Waterman 5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Henry Cook 485f1b7bd7 bump uncore 2015-11-16 18:14:03 -08:00
Yunsup Lee 8916c7e99c push rocket 2015-11-14 16:43:28 -08:00
Yunsup Lee 6a6371fdb6 move to new version of hardfloat 2015-11-14 14:50:13 -08:00
Howard Mao a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Colin Schmidt 97d0e195ae Merge pull request #28 from ucb-bar/yusnup 
Don't re-generate the .d files on "make clean"
 2015-11-12 00:46:21 -08:00
Palmer Dabbelt 07f0e6be94 Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
Howard Mao 6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao 11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao 31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao 55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao 149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao 51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Yunsup Lee 1e772daeea no spaces in Makefrag 2015-11-05 16:42:05 -08:00
Howard Mao cb0c2df051 update fpga-zynq 2015-11-05 10:50:13 -08:00
Howard Mao 42e7067400 bump uncore 2015-11-05 10:49:25 -08:00
Howard Mao bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao fb501e75c0 fixes for sub-block TL requests in uncore 2015-11-05 10:48:32 -08:00
Howard Mao 7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Howard Mao ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Sagar Karandikar ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity 2015-11-05 10:48:32 -08:00
Sagar Karandikar 354abf5e6b fix NSets calculation 2015-11-05 10:48:32 -08:00
Howard Mao dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao 04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Yunsup Lee 51116e0674 add 2 and 4 memory channel configs 2015-11-05 10:48:32 -08:00
Yunsup Lee 0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao 9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Colin Schmidt 032bdd0601 Merge pull request #24 from ucb-bar/regression-master 
Add a "--master" flag to the regression script
 2015-10-29 14:15:44 -07:00
Palmer Dabbelt 3d2a4ffdd6 Add a "--master" flag to the regression script 
I want to be able to test the master of riscv-gnu-toolchain against the current
RTL as part of the buildbot.  This flag takes a list of repositories (by their
submodule path) and updates those to the current master, which facilitates that
check.
 2015-10-29 14:11:26 -07:00
Howard Mao eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Yunsup Lee a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Howard Mao c3a7dcf0ab fix missing cde library dependencies in submodules 2015-10-23 15:05:19 -07:00
Colin Schmidt 854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook 9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Henry Cook 47bc193c16 added CDE library as submodule 2015-10-21 18:24:16 -07:00
Howard Mao 21f342ad42 fix typo causing L2 cache configuration to fail 2015-10-21 13:37:33 -07:00