Wesley W. Terpstra
ac886026e6
rocketchip: reduce number of type parameters
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
72a7948ad2
rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
401fd378b4
rocketchip: include devices from cbus in ConfigString
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
a73aa351ca
rocketchip: fix all clock crossings
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
89139a9492
Plic: split constants from variables used in config string
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
Wesley W. Terpstra
3df797fcab
rocketchip: replace TL1 MMIO with an example of TL2 MMIO
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
ec2d23b8b7
rocketchip: Bundle-slices need access to the outer LazyModule
...
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.
Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0dbda2f07d
rocketchip: remove obsolete pDevices used during TL1=>2 migration
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
7dc97674d6
rocketchip: include an socBus between l1tol2 and periphery ( #415 )
...
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
mwachs5
3a1d8fe482
debug: use a different form of the crossing which doesn't create an AsyncScope ( #394 )
2016-10-09 20:33:18 -07:00
Henry Cook
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
Megan Wachs
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
Andrew Waterman
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Megan Wachs
449d689a4e
jtag: Connect the JTAG DTM side of the synchronizer!
2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0
print out assigned inerrupt ranges
2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4
assign interrupt ranges deterministically
2016-09-29 11:59:32 -07:00
Howard Mao
c45cc76cef
Get rid of remaining MemIO code
...
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
Wesley W. Terpstra
3926cb936b
rocketchip: add pbus width and AMO With classes ( #357 )
2016-09-27 15:52:13 -07:00
Howard Mao
71a9c78e4b
add WidthAdapter from AXI slave to Coreplex TL slave
2016-09-27 12:48:01 -07:00
Howard Mao
7d6fb950b6
Give TileLink IDs more sensible names
...
* Outermost -> MCtoEdge
* MMIO_Outermost -> MMIOtoEdge
Then the corresponding parameters objects are
* L1toL2 -> innerParams
* L2toMC -> outerMemParams
* L2toMMIO -> outerMMIOParams
* MCtoEdge -> edgeMemParams
* MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01
move memory width adapter from coreplex to periphery
2016-09-27 12:48:01 -07:00
Howard Mao
e36441a046
use correct parameters object for MMIO width adapter
2016-09-27 12:48:01 -07:00
Howard Mao
201e247f73
Factor coreplex IO connection into separate trait ( #350 )
...
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.
The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
Howard Mao
6316ebd58f
make naming of L2toMC parameter object consistent between coreplex and periphery
2016-09-26 17:28:21 -07:00
Howard Mao
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
Wesley W. Terpstra
dd9558f45d
rocketchip: generate GraphML output
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
14cd39e045
rocketchip: rename identically names devices with _%d ( #340 )
...
* rocketchip: rename identically names devices with _%d
If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...
* junctions: blow if duplicates add to addrmap
2016-09-26 13:05:49 -07:00
mwachs5
77a0f76289
Cleanup jtag dtm ( #342 )
...
* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
Wesley W. Terpstra
d175bb314d
Periphery: make bus width and arithmetic atomics configurable ( #337 )
2016-09-23 15:25:58 -07:00
Wesley W. Terpstra
a421469754
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
...
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.
For example, this:
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
Howard Mao
22053289ef
fix typo rv64iu -> rv64ui
2016-09-22 17:33:35 -07:00
Henry Cook
673efb400d
Merge branch 'master' into unittest-config
2016-09-22 16:20:53 -07:00
Henry Cook
1e54820f8c
Merge remote-tracking branch 'origin/master' into unittest-config
2016-09-22 16:03:51 -07:00
Henry Cook
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
Wesley W. Terpstra
0a3718881f
rocketchip: re-enable testing of atomics
2016-09-22 15:18:54 -07:00
Henry Cook
83c08a931d
[WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator
2016-09-22 14:57:18 -07:00
Henry Cook
47c5d1a992
[WIP] Move RocketTestSuite generation into RocketchipGenerator
2016-09-22 14:31:45 -07:00
Yunsup Lee
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd
rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Henry Cook
ed91e9a89b
Merge remote-tracking branch 'origin' into testharness-refactor
2016-09-20 13:03:21 -07:00
Henry Cook
b97a0947a9
[rocketchip] enable piecewise Generator output
2016-09-20 12:57:56 -07:00
Andrew Waterman
3b38736a8e
Make BaseTopModule and BaseTopModule abstract
...
They aren't meant to be directly instantiated.
2016-09-19 17:18:35 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Henry Cook
df442ed82c
[rocketchip] avoid pending merge conflict]
2016-09-19 13:24:01 -07:00
Henry Cook
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
Henry Cook
7b8aa6c839
[rocketchip] split out Base and Example tops
2016-09-19 11:00:13 -07:00
Wesley W. Terpstra
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
01c1886b9d
Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
Wesley W. Terpstra
c70045b8b3
Utils: express cacheability from TL2 to TL1
2016-09-17 00:16:40 -07:00
Wesley W. Terpstra
e3d2bd3323
Top: print memory region properties, RWX [C]
2016-09-17 00:16:00 -07:00
Wesley W. Terpstra
5c858685aa
Utils: support managers with multiple addresses
2016-09-16 18:03:49 -07:00
Wesley W. Terpstra
a9382b3116
Periphery: test bench looks for "testram"
2016-09-16 17:47:20 -07:00
Wesley W. Terpstra
b5ce6150c7
Periphery: dynamically create address map + config string for TL2
2016-09-16 17:28:47 -07:00
Richard Xia
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
Andrew Waterman
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
e1d7f6d7df
PRCI: always use bus width >= XLen
2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
Jack Koenig
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
Henry Cook
245f8ab76b
[util] move LatencyPipe into util
2016-09-15 13:30:34 -07:00
Henry Cook
be9ddae77f
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913
Remove Option from success flag in coreplex; just use a sane default.
2016-09-15 12:19:22 -07:00
Henry Cook
888f6a2a55
Revert "move UnitTest back into rocketchip module"
...
This reverts commit f95b8c4ec2
.
2016-09-15 11:48:09 -07:00
Howard Mao
49863944c4
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709
wrap TestHarness latency pipe in module
2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e
use named constants to set AXI resp, cache, and prot fields
2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2
move UnitTest back into rocketchip module
2016-09-14 20:51:56 -07:00
Yunsup Lee
e404bea2ee
Merge branch 'master' into move-bootrom
2016-09-14 18:58:48 -07:00
Yunsup Lee
97809b183f
refactor unittest framework
...
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
Yunsup Lee
710f1ec020
Move BootROM from Coreplex to Periphery
2016-09-14 16:09:59 -07:00
Andrew Waterman
c3ddff809b
Move PRCI from Coreplex to always-on block, where it belongs
2016-09-14 11:01:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
8142406d2e
junctions: refactor the Crossing type
2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5
crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain
2016-09-13 15:51:18 -07:00
Howard Mao
f3cdeb08c6
pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d
allow configuration of simulation memory latency
2016-09-12 12:33:50 -07:00
Yunsup Lee
fea31c7061
let GlobalAddrMap and ConfigString overridable
2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
Yunsup Lee
2c000a99da
compartmentalize Top into periphery traits
2016-09-08 02:08:57 -07:00
Andrew Waterman
70cfd7ce13
Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
...
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Yunsup Lee
fb05f5a07f
remove parameter ExtIOAddrMapEntries ( #250 )
...
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
2016-09-07 00:05:00 -07:00
Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Andrew Waterman
6872000f5e
Merge pull request #239 from ucb-bar/move_rtc
...
Move RTC
2016-09-02 15:17:49 -07:00
Megan Wachs
af364bc7bc
Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal
2016-09-02 15:14:39 -07:00