Henry Cook
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
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Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
66489ffa13
rom+sram: add a compatible field
2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958
TLZero: include a version number
2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
e6c2d446cc
rocket: link dtim to its cpu
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
3f6d5110cd
rocket: dtim is not a dcache
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
bca3db0866
diplomacy: add RWXC permissions also to ResourceMappings
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
5436be54ff
periphery: use SimpleBus for mmio ports
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
171e1a4c05
diplomacy: add SimpleBus to describe bridges
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
0bf46edb6c
diplomacy: support reg-names in DTS output
2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
6c2b770605
plic: do not output #address-cells
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This is only needed for an interrupt-map, not an interrupt-controller.
2017-06-28 14:26:55 -07:00
Andrew Waterman
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
Andrew Waterman
8e4be40efc
Propagate wb_reg_rs2 for sfence ASID
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This would have been a bug if we supported ASIDs.
2017-06-28 02:09:18 -07:00
Andrew Waterman
2077e4190b
Make log more sensible for long-latency operations
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Show only one write to the destination register, not two.
2017-06-28 02:09:18 -07:00
Andrew Waterman
6f8fdff762
Basic L1 D$ ECC support
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Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
Andrew Waterman
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
Andrew Waterman
9c78ac4d78
Add grouped method to AugmentedUInt, like Seq.grouped
2017-06-28 02:09:18 -07:00
Andrew Waterman
8989f5654c
Add swizzle method to Encoding
2017-06-28 02:09:18 -07:00
Andrew Waterman
3e04a99f61
Refactor frontend exception passing
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Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
2017-06-28 02:09:18 -07:00
Andrew Waterman
cc2f87c214
Forbid S-mode execution from user memory
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285c81746f
2017-06-28 02:09:18 -07:00
Andrew Waterman
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
Andrew Waterman
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
Andrew Waterman
d5f80df0ae
Allow speculative I$ refill to cacheable regions
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Backpedaling on 27b143013f
2017-06-28 02:09:18 -07:00
Megan Wachs
3fc75c2714
debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W.
2017-06-27 17:40:58 -07:00
Megan Wachs
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
Megan Wachs
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
Megan Wachs
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
Megan Wachs
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
Megan Wachs
665c2a349c
Correct Debug + WFI Interactions
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1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
Zihao Yu
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
Wesley W. Terpstra
66f64a9759
tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters ( #822 )
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idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
2017-06-26 17:54:17 -07:00
Wesley W. Terpstra
8ca6c10994
tilelink2: ToAXI4 can strip off low source ID bits
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Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.
This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
2017-06-23 17:22:45 -07:00
Wesley W. Terpstra
feecfb53ed
axi4: Deinterleaver need not make a Q for an unused AXI id
2017-06-23 17:22:42 -07:00
Wesley W. Terpstra
9bea7c1c58
Merge pull request #815 from freechipsproject/reduce-others
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Reduce others
2017-06-23 12:13:48 -07:00
Wesley W. Terpstra
2d8b2f4edd
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
Henry Cook
ad4b454b49
isp: passthru based on edgesOut = edgesIn ( #814 )
2017-06-22 21:23:49 -07:00
Wesley W. Terpstra
48611266fa
diplomacy: use ReduceOthers in the RegMapper
2017-06-22 19:43:47 -07:00
Wesley W. Terpstra
11d1cb02eb
util ReduceOthers produces nlogn cost ready-valid logic
2017-06-22 19:43:20 -07:00
Jack Koenig
1f137cb9ff
Merge pull request #800 from ss2783/patch-1
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GeneratorUtils: support to elaborate a RawModule
2017-06-22 12:34:41 -07:00
Colin Schmidt
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
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* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
Henry Cook
bf431c0a53
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
Wesley W. Terpstra
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
Henry Cook
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
Henry Cook
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
Wesley W. Terpstra
bb309e573f
TLSplitter: special-case the case of no split necessary
2017-06-20 14:10:25 -07:00
