Wesley W. Terpstra 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) ... idCount <= 1 implies that no more than one transaction can be inflight, so there is no need to interlock R+W. However, when stripBits > 0, it is possible for a non-FIFO master to have > 1 idCount. In this case, we also don't need to interlock R+W.		2017-06-26 17:54:17 -07:00
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main/scala	tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822)	2017-06-26 17:54:17 -07:00