Yunsup Lee
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3edc1f42aa
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revamp the backup memory link in the vlsi backend
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2012-10-23 03:31:34 -07:00 |
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Andrew Waterman
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367b5489d1
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first crack at continuous compilation/testing flow
try it out: cd emulator; make test
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2012-10-19 04:09:07 -07:00 |
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Andrew Waterman
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1ad928cfe2
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directly integrate dramsim build
also, build it as a static library to simplify dependencies
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2012-10-18 18:59:37 -07:00 |
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Andrew Waterman
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edf0eeed01
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integrate updated rocket/uncore
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2012-10-18 17:51:41 -07:00 |
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Miquel Moreto
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6d49dc51a0
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Fixed emulator Makefile + extra info in the README file
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2012-10-16 11:06:48 -07:00 |
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Miquel Moreto
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aa3dc422b4
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Added first README file
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2012-10-15 10:54:47 -07:00 |
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Miquel Moreto
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5d75ddc553
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Added dramsim2 memory model to the emulator backend
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2012-10-14 14:06:28 -07:00 |
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Yunsup Lee
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34da073077
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fix tab
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2012-10-11 12:09:49 -07:00 |
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Huy Vo
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f67f8829e3
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new rocket + uncore tags, added uncore dependencies to Makefrag
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2012-10-10 15:44:19 -07:00 |
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Andrew Waterman
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7fd4eb6afd
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update uncore
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2012-10-09 18:05:32 -07:00 |
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Andrew Waterman
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c3236e6ee6
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add missing symlink and update uncore
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2012-10-09 17:51:33 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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Huy Vo
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8560ea6e40
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rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
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2012-10-01 19:12:18 -07:00 |
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Huy Vo
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084a0d31c3
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initial commit, all the relevant submodules
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2012-09-26 17:46:17 -07:00 |
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