riscv/rocket-chip
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1063 Commits

Author SHA1 Message Date
Howard Mao
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook
ab3814dcee Merge branch 'master' into tl2-irrevocable 2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Wesley W. Terpstra
1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881 [junctions] messed up the merge lulz 2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook
08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman
5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) 2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao
1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook
632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Henry Cook
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Wesley W. Terpstra
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Wesley W. Terpstra
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00
Wesley W. Terpstra
cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
Wesley W. Terpstra
1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Wesley W. Terpstra
66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Wesley W. Terpstra
60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Yunsup Lee
2c000a99da compartmentalize Top into periphery traits 2016-09-08 02:08:57 -07:00
Yunsup Lee
e35e7b2ee3 Fix routing in non-contiguous MMIO regions 
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
 2016-09-07 19:28:12 -07:00
Andrew Waterman
7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Colin Schmidt
254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
Andrew Waterman
23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
Andrew Waterman
02a2439222 Support a degenerate PLIC with no interrupts 
Resolves #249
 2016-09-07 11:21:13 -07:00
Andrew Waterman
70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC 
The latter is more the domain of TinyConfig.
 2016-09-07 01:58:25 -07:00
Andrew Waterman
a7f47f3c23 Reduce default BTB size 
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
 2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Yunsup Lee
fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
 2016-09-07 00:05:00 -07:00
Wesley W. Terpstra
d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Yunsup Lee
b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) 
now you can add them in any order.  there's an explicit check at the end to figure out whether there are overlapping regions.
 2016-09-06 21:53:55 -07:00
Wesley W. Terpstra
aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Yunsup Lee
56d81b0034 fix configstring printout with no memory 2016-09-06 10:40:11 -07:00
Wesley W. Terpstra
54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra
3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00
Howard Mao
a7f79aa409 get rid of TileLinkMemorySelector 2016-09-04 10:55:19 -07:00
Howard Mao
f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper 2016-09-04 10:55:19 -07:00
Howard Mao
66de89c4db allow fixed priority routing in Junctions arbiters 2016-09-04 10:55:19 -07:00
Howard Mao
efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types 2016-09-04 10:55:19 -07:00
Howard Mao
b9b79e4fb6 get rid of AtoS RTL 2016-09-04 10:55:19 -07:00
Howard Mao
f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
Yunsup Lee
a4c1942958 flatten Coreplex module hierarchy 2016-09-02 17:45:08 -07:00
Andrew Waterman
63679bb019 Add support for L1 data scratchpads instead of caches 
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
 2016-09-02 16:22:07 -07:00
Jim Lawson
dc9ae19936 Work-around for current Scala compiler "structural type loses implicits". 
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.

    [error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
    [error] possible cause: maybe a semicolon is missing before `value asOutput'?
    [error]   }.asOutput
    [error]     ^
    [error] one error found
    [error] (uncore/compile:compileIncremental) Compilation failed

This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
 2016-09-02 15:38:18 -07:00
Andrew Waterman
fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
Andrew Waterman
e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Andrew Waterman
7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable 2016-09-02 15:27:54 -07:00
Andrew Waterman
6872000f5e Merge pull request #239 from ucb-bar/move_rtc 
Move RTC
 2016-09-02 15:17:49 -07:00
Megan Wachs
af364bc7bc Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal 2016-09-02 15:14:39 -07:00
Megan Wachs
8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications 2016-09-02 11:11:40 -07:00
Andrew Waterman
c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Yunsup Lee
4a7972be31 connect testharness components via member functions (#236) 
to prevent code duplication for new testbenches
 2016-09-01 18:38:39 -07:00
Howard Mao
c66318307c no longer need to set invalidate_lr in RoCC examples 2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c tie off invalidate_lr in RoCC 2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF 2016-08-31 22:00:27 -07:00
Howard Mao
50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4 fix DecoupledTLB to handle misses appropriately 2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
SeungRyeol Lee
b1ce3b8c98 Add address map entries for exported mmio port. 2016-08-31 06:58:38 +09:00
Andrew Waterman
8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
Andrew Waterman
07d48df88a Get rid of FPU RoCC port logic when RoCC not present 
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC.  Thus, when the RoCC was not
present, it was still creating muxes.  Using ex_cp_valid instead
gets rid of them.
 2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
Andrew Waterman
9ca82dd397 reset default MulDiv config to moderately fast default 
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
 2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60 set missing port direction 
Ideally, chisel should flag this as an error.
 2016-08-29 12:31:52 -07:00
Megan Wachs
53ee54dbd1 Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself 2016-08-26 10:40:39 -07:00
Megan Wachs
41aa80c5d7 Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts 2016-08-26 09:32:36 -07:00
Ben Keller
79293f4fa2 Use a better iterator inside the DCache 2016-08-25 20:41:39 -07:00
Henry Cook
115e8edd83 Merge branch 'master' into coreplex_peripheral_interrupts 2016-08-25 17:26:56 -07:00
Henry Cook
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
Megan Wachs
428eed79a1 Allow some External Interrupts to come from Periphery 2016-08-25 14:16:33 -07:00
Megan Wachs
32118269c1 Remove } introduced in merge 2016-08-23 08:20:52 -07:00
Megan Wachs
9974626d6a Merge remote-tracking branch 'origin/master' into HEAD 
Conflicts:
	src/main/scala/rocketchip/TestHarness.scala
 2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44 fix bus axi connections in periphery 2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2 extra devices should get elaborated in a single build function 2016-08-22 11:57:15 -07:00
Scott Johnson
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
mwachs5
22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
Megan Wachs
75efc7dee7 JtagIO's DRV_TDO should be an INPUT 2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb Move files after the file reorganization 2016-08-19 16:11:41 -07:00
Megan Wachs
3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module. 
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0
 2016-08-19 16:08:31 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation 
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
 2016-08-19 16:08:17 -07:00
Howard Mao
f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Andrew Waterman
114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
Andrew Waterman
3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters 
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
 2016-08-19 12:06:17 -07:00
Colin Schmidt
0a6c05a5d8 connect top level interrupts to coreplex 2016-08-18 15:52:44 -07:00
Howard Mao
91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao
1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao
18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao
f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao
d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
David Biancolin
29600f64ec make memsize configurable 2016-08-17 16:31:34 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao
e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao
4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao
0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao
3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Howard Mao
9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao
410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Howard Mao
f04aefc95c get rid of deprecated ZynqAdapter 2016-08-02 13:14:20 -07:00
Howard Mao
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao
b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao
98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Megan Wachs
55c992bb3a Use FoldRight() instead of for loop 2016-08-01 16:56:33 -07:00
Megan Wachs
8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman
058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Howard Mao
cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao
ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao
1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao
75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Megan Wachs
c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Howard Mao
20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Wesley W. Terpstra
9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Howard Mao
e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42 Rename MulDivUnroll to MulUnroll 2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96 Create seperate Mul/Div paramters instead of UseFastMulDiv 2016-07-15 14:40:37 -07:00
Andrew Waterman
ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Howard Mao
90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao
f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao
74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4 make Comparator fit the GroundTest model 2016-06-27 16:01:32 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao
3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
ff43238e6e give DualCoreConfig L2 cache to speed up test runs 2016-06-20 17:58:26 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b return non-zero exit codes when an assertion fires 
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
 2016-05-18 12:57:58 -07:00
Andrew Waterman
684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Andrew Waterman
6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao
dfcb73b6c9 groundtest only needs to write to a single tohost 2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5 fix CacheFillTest 2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa add default cases to configs that use CDEMatchError 
this avoids filling in the stack trace every time
a config doesn't contain the parameter
 2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969 put memory into the address map and no longer use MMIOBase 2016-04-21 18:53:16 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs 
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
 2016-04-12 15:39:15 -07:00
Andrew Waterman
b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. 2016-04-01 18:09:00 -07:00
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao
1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
d697559754 Correct the polarity of the non-backup-memory HTIF 
This fails in FIRRTL because <> has polarity now.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
c989ec5813 Fix the SCR file for Chisel 3 2016-03-21 11:55:40 -07:00
Howard Mao
e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Eric Love
4fc2a14a63 Fix MIF bug that cuts off upper xact id bits 2016-03-16 13:50:30 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Andrew Waterman
7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao
5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata 
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
 2016-03-01 13:03:24 -08:00
John Wright
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64 
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
 2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781 Add an 8-channel backup memory port config 
Now that the backup memory port works I want to test it.
 2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0 Fix the backup memory port on multiple-channel configs 
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
 2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port 
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
 2016-02-27 10:46:56 -08:00
Yunsup Lee
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
Colin Schmidt
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/... 
This uses the compiled tests in RISCV, which match the rest of the toolchain.
 2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
Colin Schmidt
0c575403af only use a single asm test and 1 bmark for memtest 2016-02-22 09:36:53 -08:00
Howard Mao
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab Allow the number of memory channels to be picked at runtime 
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
 2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Christopher Celio
c1b4d9372f Revert "add new parameters for new SCR file" 
This reverts commit 4dad5b8b32.

The commit breaks the build.
 2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a Revert "use singleton for global" 
This reverts commit 4d0f941de3.

The commit breaks the build.
 2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3 use singleton for global 2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes 
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
 2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one 
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
 2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao
c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Howard Mao
806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao
8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Howard Mao
0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao
f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao
cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Howard Mao
c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
Howard Mao
40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao
23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Howard Mao
ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Andrew Waterman
5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao
149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity 2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b fix NSets calculation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674 add 2 and 4 memory channel configs 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao
eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Howard Mao
c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609 L2 rowBits param bugfix 2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale) 2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) 2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5 Merge branch 'param-refactor-tl' 2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Christopher Celio
c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Andrew Waterman
700910adff Chisel3 compatibility fix for <> 2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6 Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7) 2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). 
Bump all submodules.
 2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d add zscale programs 2015-07-27 19:06:06 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Yunsup Lee
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Yunsup Lee
4c7c3f5bb2 add test generate for ZscaleTop 2015-07-14 16:26:28 -07:00
Henry Cook
76046c52fe Cleanup testing rv64uf 2015-07-13 18:58:58 -07:00
Henry Cook
302cd3e638 Added BuildZscale param for use in Top and makefrag generation 2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d rename Configs source 2015-07-09 15:04:11 -07:00
Yunsup Lee
09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff Added some multicore/multibanks named ChiselConfigs 2015-07-06 18:21:06 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Yunsup Lee
702ddabe26 add ExampleSmallConfig for README 2014-10-07 02:07:59 -07:00
Yunsup Lee
e25d420155 Improve ChiselConfig composability; bump chisel 2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65 Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays) 2014-10-06 13:40:35 -07:00
Henry Cook
122733b3a9 file name consistency 2014-10-06 13:37:38 -07:00
Henry Cook
0b5f23a209 Streamlined uncore for release 2014-10-06 13:37:15 -07:00
Adam Izraelevitz
15fb4730ec Add BuildTile parameter for Tile 
Conflicts:
	rocket
 2014-09-25 06:50:45 -07:00
Henry Cook
7398b00d93 dir supplied by function 2014-09-25 06:50:41 -07:00
Henry Cook
5a840c5520 support for multiple tilelink paramerterizations in same design 2014-09-25 06:50:30 -07:00
Donggyu Kim
eb384f6461 new RocketChipBackend implementation 2014-09-25 06:47:12 -07:00
Scott Beamer
f2ca887de3 better fpga configs 2014-09-25 06:47:03 -07:00
Donggyu Kim
4fe48f5a0a bump chisel 2014-09-25 06:46:58 -07:00
Donggyu Kim
60d90f5230 recover collectNodesIntoComp in Backends.scala 2014-09-25 06:46:50 -07:00
Donggyu Kim
a53091b40f remove collectNodesIntoComp from Backends.scala 2014-09-25 06:46:27 -07:00
Scott Beamer
f4e6cd75ab turn off fpu for default fpga config. 
a larger fpga can use defaultconfig
 2014-09-25 06:46:16 -07:00
Yunsup Lee
09de2e2794 compute number of outstanding misses for DRAMSideLLCNull 2014-09-12 18:09:38 -07:00
Yunsup Lee
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee
c98afa1fea turn off DRAMSideLLC 2014-09-11 22:10:25 -07:00
Yunsup Lee
b5a64487eb turn off DRAMSideLLC 2014-09-11 22:07:44 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
6b6bdd2b83 decommission Slave top-level module for fpga build 2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Henry Cook
ae05125f29 Adjustements to top-level parameters and knobs for hwacha 2014-09-07 17:57:33 -07:00
Henry Cook
4126678c9d Merge branch 'dse' 
Conflicts:
	rocket
	uncore
 2014-09-06 06:59:14 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Yunsup Lee
7734285507 forgot to comment out hwacha 2014-09-01 09:01:36 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Henry Cook
78ab83d224 refactor fpga top/config 2014-08-28 13:07:54 -07:00
Henry Cook
bf356b9cb4 Refactor to combine fpga and vlsi tops, part 1 2014-08-24 19:30:53 -07:00
Henry Cook
a41d55b643 Final parameter refactor. 2014-08-23 01:26:03 -07:00
Scott Beamer
63b62394d9 added l2 to fpga 
with new chisel & uncore, it goes into brams
 2014-08-20 15:41:07 -07:00
Henry Cook
1563c1bb36 Fixed cache params. Asm and bmark tests pass. 2014-08-12 15:00:54 -07:00
Henry Cook
7f07771600 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Adam Izraelevitz
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Henry Cook
434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Henry Cook
ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00
Henry Cook
fbf6e44376 fix connection error in fpga uncore 2014-04-24 11:58:59 -07:00
Henry Cook
cfd6748318 patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) 2014-04-21 17:26:33 -07:00
Henry Cook
2cb4dbae39 Refactored uncore constants and tilelink data 2014-04-10 13:19:50 -07:00
Henry Cook
5a5f69bfca finished uncore constant/tilelink data refactor 2014-04-10 13:13:46 -07:00
Andrew Waterman
817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Henry Cook
56f515c255 first steps in uncore constant/tilelink data refactor 2014-03-30 09:21:08 -07:00
Andrew Waterman
d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Yunsup Lee
e20d50436a committed in the wrong directory, meant to commit in the hwacha directory 2014-03-01 00:01:35 -08:00
Yunsup Lee
8c459df3b6 flush deck when xcpt occurs, fixes remaining p test bugs 2014-02-28 22:50:34 -08:00
Stephen Twigg
755293d785 Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). 2014-02-14 10:12:09 -08:00
Andrew Waterman
11e69a73cd Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
Stephen Twigg
8c96e27ca6 Merge branch 'master' into hwacha-port 
Mostly Stable version that is passing tests
 2014-02-04 17:20:28 -08:00
Henry Cook
382fa0ef27 cleanups supporting uncore hierarchy 2014-01-31 16:03:58 -08:00
Stephen Twigg
e7ee94bcc8 Merge branch 'master' into hwacha-port 2014-01-21 15:23:05 -08:00
Stephen Twigg
ee0c4ca291 Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) 2014-01-21 14:48:04 -08:00
Andrew Waterman
6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman
a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Stephen Twigg
e50c5180cd Merge branch 'master' into hwacha 2013-11-14 16:03:55 -08:00
Yunsup Lee
1d6d4b4e96 move htif to uncore 2013-11-07 13:19:19 -08:00
Yunsup Lee
c810847761 hookup all memory ports 2013-11-05 17:12:25 -08:00
Stephen Twigg
7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
Stephen Twigg
36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Huy Vo
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Andrew Waterman
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook
b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
Stephen Twigg
6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Yunsup Lee
ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee
76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee
0884bc9789 fix DRAMSideLLCNull entries 2013-08-24 13:20:38 -07:00
Yunsup Lee
1e3ac0afa9 back to NTILES=1 2013-08-24 13:10:30 -07:00
Henry Cook
b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook
85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Henry Cook
6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
 2013-08-15 16:39:30 -07:00
Henry Cook
784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook
9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Huy Vo
cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Henry Cook
11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook
199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00
Henry Cook
4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
Henry Cook
2796de01bf new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:41:27 -07:00
Henry Cook
896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook
c06cbf523b Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
Henry Cook
6a69d7d7b5 pass closure to generate bank addr 2013-05-23 14:58:19 -07:00
Andrew Waterman
d825c9d6e9 make fpga Makefile work with updated Makefrag 2013-05-02 05:09:45 -07:00
Andrew Waterman
cfa86dba4f add FPGA test bench 
The memory models now support back pressure on the response.
 2013-05-02 04:59:32 -07:00
Andrew Waterman
50bd9a08a7 resynchronize fpga uncore 2013-05-01 01:12:47 -07:00
Yunsup Lee
93df795e48 change LLC leaf SRAM size 2013-04-22 11:06:50 -07:00
Huy Vo
2ac3fd5306 get rid of init_node 2013-04-20 01:36:32 -07:00
Huy Vo
0d87e3bacc fixed init pin generation 2013-04-20 00:38:01 -07:00
Henry Cook
a01cdf95fd tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps 2013-04-10 13:53:27 -07:00
Henry Cook
16ad8a7e9c Fixes after merge 2013-03-25 19:14:38 -07:00
Andrew Waterman
8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
eec590c1bf Added support for multiple L2 banks. Moved tile IO queueing. 2013-03-25 17:01:46 -07:00
Henry Cook
806f897fc4 nTiles -> nClients in LogicalNetworkConfig 2013-03-25 17:01:46 -07:00
Andrew Waterman
ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
cf76665d09 writebacks on release network pass asm tests and bmarks 2013-03-25 17:01:46 -07:00
Henry Cook
a0dc8d52d6 using new network and l2 controller 2013-03-25 17:01:46 -07:00
Yunsup Lee
9efe71412f add DRAMSideLLCNull 2013-03-19 00:43:34 -07:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Yunsup Lee
516a64f576 commit vec=true 2013-01-22 20:24:33 -08:00
Henry Cook
bb5c465bb3 Switched back to old, better-tested hub on master 2013-01-22 19:57:31 -08:00
Henry Cook
5b82d72eb7 New TileLink bundle names 2013-01-21 17:19:07 -08:00
Henry Cook
72bba81a76 now using single-ported coherence master 2013-01-16 23:58:24 -08:00
Henry Cook
e33648532b Refactored packet headers/payloads 2013-01-15 15:57:06 -08:00
Henry Cook
a922b60152 Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor 2013-01-07 14:23:49 -08:00
Henry Cook
f2cef8d8d2 new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore 2013-01-07 14:19:55 -08:00
Andrew Waterman
fd727bf8aa add some of the zedboard fpga infrastructure 
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
 2013-01-06 03:58:10 -08:00
Henry Cook
d0805359a5 Refactored uncore conf 2012-12-13 11:46:29 -08:00
Henry Cook
1d7f1a8182 Removed dummy tile instances 2012-12-12 16:44:03 -08:00