Henry Cook
57edd7facf
subsystem: streamline toTile and fromTile attachment
2018-02-21 14:43:47 -08:00
Wesley W. Terpstra
ef3addee7b
diplomacy: put full module + instance path into graphml Description
2018-02-21 14:43:47 -08:00
Henry Cook
62aee56807
diplomacy: base instance names on ValName and module names on className
2018-02-21 14:43:47 -08:00
Henry Cook
3f436a7612
subsystem: new bus attachment api
2018-02-21 14:43:47 -08:00
Henry Cook
8462ea3d5b
coreplex => subsystem
2018-02-21 14:42:24 -08:00
Andrew Waterman
8998a97ea1
Preserve WithRV32 behavior: FLEN = 32
2018-02-20 18:28:47 -08:00
Andrew Waterman
1dc1e2c099
support testing RV32D configs
2018-02-20 16:16:39 -08:00
Andrew Waterman
d4fb7ad6a2
DefaultRV32Config should provide fdiv/fsqrt
...
This is a holdover from before we had built the functional unit.
2018-02-20 16:16:39 -08:00
Andrew Waterman
b487448961
Add FPUParams.fLen option, decoupled from xLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
5e35015651
Minor Rocket fixes to support fLen != xLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
bd29184e11
debug: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
62f9b84439
plic: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
52e22a1dd8
clint: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
1bac2cbdf8
Give Rocket priority over DTIM TL port
...
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline. Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads. Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
Megan Wachs
5affd3bec2
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 10:24:12 -08:00
Megan Wachs
cf7cd03d64
Merge pull request #1239 from freechipsproject/reduce_debug_flags
...
Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
Megan Wachs
d72abb7a12
Debug: revert change to how flags are named
2018-02-15 21:49:32 -08:00
Wesley W. Terpstra
dcfbdabe60
CacheCork: better document edge conditions
2018-02-15 19:14:30 -08:00
Wesley W. Terpstra
ecd069dca4
tilelink: allow FIFO caches
...
Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
Wesley W. Terpstra
acecc407a5
HellaCache: we do NOT really support probe below the block size!
...
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
Megan Wachs
c34b940d9a
ElaborationArtefacts: revert unintentional change
2018-02-15 14:23:54 -08:00
Megan Wachs
e0c3b22d61
RegFieldDesc: same string used to insert/compare
2018-02-15 14:23:27 -08:00
Megan Wachs
b95f68447f
RegFieldDesc: Prevent different RegField JSONS from overwriting eachother.
2018-02-15 14:01:47 -08:00
Megan Wachs
64d3731e45
RegFieldDesc: don't put characters into names that need to be sanitized
2018-02-15 13:25:06 -08:00
Megan Wachs
197699b93a
Debug: don't need to fully populate flags array
2018-02-15 13:23:51 -08:00
Wesley W. Terpstra
fa412246b3
Error: don't be an exception wrt. caching
...
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.
Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
Megan Wachs
de91672e9a
RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields
2018-02-12 08:32:52 -08:00
Megan Wachs
7bf0121f07
PLIC: correct some descriptions
2018-02-12 08:31:29 -08:00
Megan Wachs
08acbe1a29
RegFieldDesc: Clean up both descriptions and JSON presentations
2018-02-11 23:57:57 -08:00
Megan Wachs
5ab4204e8a
RegField: the JSON will just leave things out of type None
2018-02-11 22:51:36 -08:00
Megan Wachs
3b44f380d8
TLRegMapper: emit a JSON file describing the register fields
2018-02-11 22:51:36 -08:00
Megan Wachs
256f8ffc6b
Clint: Annotate regmap with RegFieldDesc
2018-02-11 21:33:09 -08:00
Megan Wachs
718c88a8f9
PLIC: Annotate regmap with RegFieldDescs
2018-02-11 21:05:17 -08:00
Megan Wachs
13b120fb01
Debug: Annotate regmaps with RegFieldDescs
2018-02-10 20:11:24 -08:00
Megan Wachs
7abf6e1c8a
RegMapper: Update cover props to use new RegFieldDesc objects
2018-02-10 13:17:38 -08:00
Megan Wachs
4ab1585a78
Register Field: Add a more verbose description object
...
Add versions of the RegField functions to take it in, and
update Example device to use it.
2018-02-10 13:17:18 -08:00
Henry Cook
fe277cf6f0
Merge branch 'master' into auto-plusargs
2018-02-06 18:38:44 -08:00
Andrew Waterman
9f6d586e8c
Add PLIC covers ( #1229 )
...
* Add another FPU hazard cover
* Add some PLIC covers
2018-02-06 17:33:33 -08:00
Andrew Waterman
efc6c9cbd3
Let user of CSRFile decide when to set tval
...
I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
Andrew Waterman
a59fc3bdaa
Teach MulDiv to do either mul-only or div-only by setting unroll=0
2018-02-06 14:03:17 -08:00
Andrew Waterman
69441930b5
Rationalize ALU function encoding
...
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
solomatnikov
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
Henry Cook
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
Henry Cook
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
Henry Cook
46751bedeb
config: MapParameters are back in style
2018-01-30 11:52:44 -08:00
Jacob Chang
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
Andrew Waterman
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
Andrew Waterman
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
...
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
Andrew Waterman
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
Jacob Chang
a749326deb
Add cover points to registers ( #1208 )
2018-01-24 21:37:24 -08:00
