riscv/rocket-chip
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Author SHA1 Message Date
Andrew WatermanandGitHub 936096dd42 Merge pull request #826 from freechipsproject/tlb2 
Various memory system improvements
 2017-06-28 13:51:24 -07:00
Andrew WatermanandGitHub 72c46e6c05 Merge pull request #818 from sashimi-yzh/faster-verilator-compile 
emulator,Makefile-verilator: add --output-split-cfuncs flag
 2017-06-26 11:39:42 -07:00
Andrew WatermanandGitHub f396b4142d Merge pull request #806 from freechipsproject/mulh 
Improve integer mul/div
 2017-06-20 13:01:16 -07:00
Andrew WatermanandGitHub 4a24e9a6c6 Merge pull request #792 from freechipsproject/fix-fdiv 
Fix FPU control bug for div/sqrt
 2017-06-09 18:27:19 -07:00
Andrew WatermanandGitHub e69badb205 Merge pull request #791 from freechipsproject/tlb 
Fix I$ reset regression
 2017-06-09 15:49:25 -07:00
Andrew WatermanandGitHub 5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew WatermanandGitHub 8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Andrew WatermanandGitHub d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Andrew WatermanandGitHub efce8f06b8 Merge pull request #769 from freechipsproject/new-div-sqrt 
Incorporate new div/sqrt unit
 2017-06-03 03:58:52 -07:00
Andrew WatermanandGitHub 618468a06b Make plusarg_reader default args work with VCS (#765) 
Resolves #764
 2017-05-24 21:38:56 -07:00
Andrew WatermanandHenry Cook dbc5e7c494 Add TLB miss performance counters (#762) 2017-05-23 12:52:25 -07:00
Andrew WatermanandHenry Cook b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Andrew WatermanandGitHub 3a9bbd7e58 Merge branch 'master' into vectored-stvec 2017-05-08 14:08:09 -07:00
Andrew WatermanandGitHub e21b74c232 Merge pull request #724 from ucb-bar/rvc-speculative 
Fix RVC/uncacheable instruction memory performance bug
 2017-05-03 18:48:49 -07:00
Andrew WatermanandYunsup Lee 4efcb5a139 Increase frontend decoupling (#722) 
Reduce pathological RVC stalls
 2017-05-03 07:54:46 -07:00
Andrew WatermanandYunsup Lee d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew WatermanandGitHub 9b688ce7e2 Merge pull request #707 from ucb-bar/itim 
ITIM
 2017-04-28 02:55:01 -07:00
Andrew WatermanandWesley W. Terpstra 8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew WatermanandHenry Cook 915697cb09 Fix FEQ flag generation (#479) 
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
 2016-12-06 11:54:29 -08:00
Andrew Waterman a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
Andrew Waterman b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman 87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman 2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman 94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman 6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00