Howard Mao
5392219d86
bump riscv-tools
2016-10-07 15:50:43 -07:00
mwachs5
4c49fef242
Merge pull request #388 from ucb-bar/cp-safer-crossings
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tilelink2: split isolation gates by direction
2016-10-07 13:45:23 -07:00
Wesley W. Terpstra
e5ac0f717f
tilelink2: split isolation gates by direction
2016-10-07 12:03:43 -07:00
Albert Ou
ad618fd55d
plic: Fix bit extraction
2016-10-06 18:05:03 -07:00
Andrew Waterman
b1c777c7a2
Fix PLIC enable bit access for #ints >= tlDataBits
2016-10-06 16:21:14 -07:00
Andrew Waterman
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
Jacob Chang
fe641c14a1
tilelink2: Add support for different noise generator in fuzzer ( #386 )
2016-10-06 13:20:13 -07:00
Andrew Waterman
5980dc160f
Don't allow multiple entries for same PC in BTB
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Necessary for RVC forward-progress guarantee.
2016-10-06 11:30:45 -07:00
Jim Lawson
9b8e8a8b9e
Add sbt-unidoc plugin; bump sbt-buildinfo version. ( #385 )
2016-10-06 10:48:11 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
4f6eb38eeb
Enable Verilator parallel builds
2016-10-04 22:29:39 -07:00
Andrew Waterman
6472d4c245
Print Verilator random seed when +verbose is passed
2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d
Explicitly zap some S-mode CSRs when not using S-mode
2016-10-04 22:29:39 -07:00
Andrew Waterman
968851f7e3
Default to configurable priorities
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up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
mwachs5
e952f8f222
asyncqueue: Fix typo in the Async Queue ( #381 )
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* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.
* asyncqueue: Typo in the typo fix
2016-10-04 21:02:06 -07:00
Andrew Waterman
064c9ebdc6
Don't report I$ fetch faults on TLB misses!
2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b
Improve back-to-back integer multiplication performance
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More exact hazard checking in the decode stage avoids a pipeline flush.
2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
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This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
Yunsup Lee
23c8b06d4a
use $urandom as seed for $random
2016-10-03 17:56:30 -07:00
Yunsup Lee
62954d543e
correctly initialize the active flag
2016-10-03 17:56:30 -07:00
Wesley W. Terpstra
6ec2e7c5bd
tilelink2: Legacy should preserve the access size ( #378 )
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* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
72e8c6f589
Merge pull request #379 from ucb-bar/axi-prefactor
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Axi prefactor
2016-10-03 16:49:37 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303
tilelink2: Nodes should accept full PortParameters
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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf
graphML: CTO's like colour
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084
LazyModule: output final verilog Module name
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
Yunsup Lee
5ff3d3d61c
correctly initialize with seed
2016-10-02 17:31:32 -07:00
Wesley W. Terpstra
52c1a053ff
tilelink2 RegisterRouter: test fully Decoupled behaviour
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4
tilelink2 RegisterCrossing: Queues go from RV to Irrevocable
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AsyncQueue is still a Queue.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
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RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
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If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
Andrew Waterman
e0188f8aa4
Don't implicitly fence on CSR instructions
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CSRs that have an effect on I/O should use an explicit FENCE.
2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
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The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
mwachs5
784f0cf0b6
Merge pull request #370 from ucb-bar/move_clint_and_plic
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clint & plic: Move the default addresses
2016-10-01 16:18:54 -07:00
Megan Wachs
28eba9b5ac
clint/plic: Move the default addresses
2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
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* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
891a253bee
Merge pull request #367 from ucb-bar/tl2-isolation
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Tl2 isolation
2016-09-30 02:19:44 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Howard Mao
a1fa0733e5
Merge pull request #366 from ucb-bar/slowio-change
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Change the configuration interface of SlowIO
2016-09-29 23:19:53 -07:00
Howard Mao
4b86802b1a
change the configuration interface of SlowIO
2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
8730887baa
Merge pull request #364 from ucb-bar/tl2-async-nodes
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Tl2 async nodes
2016-09-29 18:18:31 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
